Modify

Opened 8 years ago

Closed 8 years ago

Last modified 4 years ago

#6532 closed defect (fixed)

Ar7 serial port still broken, Actiontec m1000 (qwest build)

Reported by: anonymous Owned by: florian
Priority: highest Milestone: Barrier Breaker 14.07
Component: kernel Version: Trunk
Keywords: ar7 serial printk earlyprintk Cc:

Description

On my device this bug still isn't fixed, and since there hasn't been any action in OVER 8 MONTHS... I'm opening a new bug

/ticket/3123.html

More information about the device and my issues with it...
https://forum.openwrt.org/viewtopic.php?pid=100851

Oddly, one time I was able to disable printk (the make kernel_menuconfig option no longer shows me it; something is hard-requesting it) and everything dumped out after the serial console registered, right up to other issues.

Attachments (6)

ar7-serial-fix.patch (527 bytes) - added by Michael J Evans <mjevans1983@…> 8 years ago.
Fix uart setup by supplying the correct flags in AR7's platform.c
actiontec-m1000-boot (128.0 KB) - added by Michael J Evans <mjevans1983@…> 8 years ago.
The unaltered boot-loader for the m1000 (8MB 64KB loader, 64KB blocks flash device)
mtd1.0x480.hex (5.6 KB) - added by Michael J Evans <mjevans1983@…> 8 years ago.
m1000 env block from 0x0 to 0x480 (offset starts at 128K in to flash)
001-detect_psbl_set_uart_autoconf.patch (2.0 KB) - added by florian 8 years ago.
Attempt to detect a PSBL bootloader and set the right UART flags accordingly.
001-detect_psbl_set_uart_autoconf-reworked-2.6.32.12.patch (5.5 KB) - added by Michael J Evans <mjevans1983@…> 8 years ago.
M1000 serial console patch - updated + reworked
970-clock-init-race-fix.patch (857 bytes) - added by Michael J Evans <mjevans1983@…> 8 years ago.
target/linux/ar7/patches-2.6.32/970-clock-init-race-fix.patch

Download all attachments as: .zip

Change History (31)

Changed 8 years ago by Michael J Evans <mjevans1983@…>

Fix uart setup by supplying the correct flags in AR7's platform.c

comment:1 Changed 8 years ago by Michael J Evans <mjevans1983@…>

One issue down...

Booting...
Linux version 2.6.30.10 (aeon@mainline) (gcc version 4.3.3 (GCC) ) #1 Thu Jan 21 02:17:43 PST 2010
console [early0] enabled
CPU revision is: 00018448 (MIPS 4KEc)
Clocks: Sync 2:1 mode
Clocks: Setting CPU clock
Adjusted requested frequency 211000000 to 211968000
Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
Clocks: Setting DSP clock
Clocks: base = 25000000, frequency = 105984000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
Clocks: Setting USB clock
Adjusted requested frequency 48000000 to 47863741
Clocks: base = 105984000, frequency = 48000000, prediv = 1, postdiv = 31, postdiv2 = -1, mul = 14
TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x11
Determined physical RAM map:

memory: 01000000 @ 14000000 (usable)

Initrd not found or empty - disabling initrd
Zone PFN ranges:

Normal 0x00014000 -> 0x00015000

Movable zone start PFN for each node
early_node_map[1] active PFN ranges

0: 0x00014000 -> 0x00015000

Built 1 zonelists in Zone order, mobility grouping off. Total pages: 4064
Kernel command line: rootfstype=squashfs,jffs2 console=ttyS0,9600n8
Primary instruction cache 16kB, VIPT, 4-way, linesize 16 bytes.
Primary data cache 8kB, 4-way, VIPT, no aliases, linesize 16 bytes
NR_IRQS:256
PID hash table entries: 64 (order: 6, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Memory: 12416k/16384k available (2171k kernel code, 3968k reserved, 406k data, 128k init, 0k highmem)
Calibrating delay loop... 211.35 BogoMIPS (lpj=1056768)
Mount-cache hash table entries: 512
net_namespace: 1008 bytes
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
NET: Registered protocol family 1
squashfs: version 4.0 (2009/01/31) Phillip Lougher
Registering mini_fo version $Id$
JFFS2 version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
msgmni has been set to 24
alg: No test for stdrng (krng)
io scheduler noop registered
io scheduler deadline registered (default)
Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
erial8250: ttyS0 at MMIO 0x8610e00 (irq = 15) is a XScale

console handover: boot [early0] -> real [ttyS0]

Fixed MDIO Bus: probed
cpmac-mii: probed
eth0 (): not using net_device_ops yet
cpmac: device eth0 (regs: 08610000, irq: 27, phy: 1:1f, mac: 00:15:05:a2:24:34)
physmap platform flash device: 00800000 at 10000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank

Amd/Fujitsu Extended Query Table at 0x0040

Unknown Amd/Fujitsu Extended Query version 0.0.

gen_probe: No supported Vendor Command Set found
physmap-flash physmap-flash.0: map_probe failed
ar7_wdt: timer margin 59 seconds (prescale 65535, change 48480, freq 52992000)
Registered led device: status
TCP westwood registered
NET: Registered protocol family 17
Bridge firewalling registered
802.1Q VLAN Support v1.8 Ben Greear <greearb@…>
All bugs added by David S. Miller <davem@…>
VFS: Cannot open root device "<NULL>" or unknown-block(0,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
Rebooting in 3 seconds..
Basic POST completed... Success.
Last reset cause: Software reset (memory controller also reset)

comment:2 Changed 8 years ago by florian

  • Owner changed from developers to florian
  • Status changed from new to assigned

I will have a test at your patch just to make sure it does not break other boards, but otherwise it looks sane to me.

comment:3 Changed 8 years ago by florian

UPF_AUTOCONF is actually breaking console on my WAG54Gv2 so I only applied UPF_IOREMAP in r19374. I assume that UPF_AUTOCONF is the flag that fixes your problem, but it breaks other so we need to find a solution.

comment:4 Changed 8 years ago by anonymous

What bootloader is your device using? Mine has some version of psbl (I over-wrote the string trying to apply a fix which failed, and lost the backup before I had a way of accessing the serial console and restoring things properly.)

If our bootloaders differ than the solution is obvious; control the options in question by specifying the platform and bootloader.

comment:5 Changed 8 years ago by florian

My device uses adam2. Our main problem is to have a single kernel approach for each and every single device we support such that we do not rely on building the same kernel multiple times for multiple devices. Can you post the bootloader environment variables, prId and any other relevant information that could help me identify your device properly?

Thanks.

Changed 8 years ago by Michael J Evans <mjevans1983@…>

The unaltered boot-loader for the m1000 (8MB 64KB loader, 64KB blocks flash device)

comment:6 Changed 8 years ago by Michael J Evans <mjevans1983@…>

Unfortunately many months ago before I saved a proper backup of things I altered several variables trying to somehow 'fix' the part-way installed OpenWRT I was trying at the time so I could either complete it, or use the factory restore: both of which failed. I had to buy a replacement modem at a local store.

These are the current variables from the backup I made once OpenWRT loaded and I could get at the areas that weren't yet touched by it.

strings mtd1

TIENV0.8
0x301
SerialNumber
none
0x01000000
0x00800000
9600,n,8,1,hw
9600,n,8,1,hw
AEIBootVersion
(psbl)
mtd2
0x90000000,0x90020000
mtd3
0x90020000,0x90030000
mtd4
0x907e0000,0x907f0000
mtd7
0x907f0000,0x90800000
192.168.0.1
DSL_FEATURE_CNTL_0
0x0000020C
vcc_encaps0
vcc_encaps1
vcc_encaps2
vcc_encaps3
vcc_encaps4
vcc_encaps5
vcc_encaps6
vcc_encaps7
modulation
211968000
211968000
105984000
m:f:"mtd1"
usb_vid
0x1668
usb_pid
0x6010
ProductID
M1000
HWRevision
DSL_PHY_CNTL_0
0x00100800
defaults
00:15:05:--cut--
WLAN_HWADDR
00:15:05:--cut--
00:15:05:--cut--
00:15:05:--cut--
00:15:05:--cut--
connection0
bootloaderVersion
(Everything after this point is probably altered by me...)

hexdump -C -n $((0x480)) mtd1
00000000 54 49 45 4e 56 30 2e 38 00 ff ff ff ff ff ff ff |TIENV0.8........|
00000010 22 ff a1 fd 01 30 78 33 30 31 00 ff ff ff ff ff |"....0x301......|
00000020 00 fd 87 f8 02 53 65 72 69 61 6c 4e 75 6d 62 65 |.....SerialNumbe|
00000030 72 00 6e 6f 6e 65 00 ff ff ff ff ff ff ff ff ff |r.none..........|
00000040 1e ff b1 fe 01 30 00 ff ff ff ff ff ff ff ff ff |.....0..........|
00000050 02 ff d4 fc 01 30 78 30 31 30 30 30 30 30 30 00 |.....0x01000000.|
00000060 03 ff cc fc 01 30 78 30 30 38 30 30 30 30 30 00 |.....0x00800000.|
00000070 04 fe c5 fb 02 39 36 30 30 2c 6e 2c 38 2c 31 2c |.....9600,n,8,1,|
00000080 68 77 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |hw..............|
00000090 05 ff c4 fb 02 39 36 30 30 2c 6e 2c 38 2c 31 2c |.....9600,n,8,1,|
000000a0 68 77 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |hw..............|
000000b0 00 fd 27 f9 02 41 45 49 42 6f 6f 74 56 65 72 73 |..'..AEIBootVers|
000000c0 69 6f 6e 00 32 2e 30 00 ff ff ff ff ff ff ff ff |ion.2.0.........|
000000d0 06 ff f7 fc 01 28 70 73 62 6c 29 00 ff ff ff ff |.....(psbl).....|
000000e0 00 fd f9 f8 02 6d 74 64 32 00 30 78 39 30 30 30 |.....mtd2.0x9000|
000000f0 30 30 30 30 2c 30 78 39 30 30 32 30 30 30 30 00 |0000,0x90020000.|
00000100 00 fd f5 f8 02 6d 74 64 33 00 30 78 39 30 30 32 |.....mtd3.0x9002|
00000110 30 30 30 30 2c 30 78 39 30 30 33 30 30 30 30 00 |0000,0x90030000.|
00000120 00 fc 80 f8 02 6d 74 64 34 00 30 78 39 30 37 65 |.....mtd4.0x907e|
00000130 30 30 30 30 2c 30 78 39 30 37 66 30 30 30 30 00 |0000,0x907f0000.|
00000140 00 fd b1 f8 02 6d 74 64 37 00 30 78 39 30 37 66 |.....mtd7.0x907f|
00000150 30 30 30 30 2c 30 78 39 30 38 30 30 30 30 30 00 |0000,0x90800000.|
00000160 0c ff cc fc 02 31 39 32 2e 31 36 38 2e 30 2e 31 |.....192.168.0.1|
00000170 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000180 00 fd 55 f7 03 44 53 4c 5f 46 45 41 54 55 52 45 |..U..DSL_FEATURE|
00000190 5f 43 4e 54 4c 5f 30 00 30 78 30 30 30 30 30 32 |_CNTL_0.0x000002|
000001a0 30 43 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |0C..............|
000001b0 00 fd 2d fa 02 76 63 63 5f 65 6e 63 61 70 73 30 |..-..vcc_encaps0|
000001c0 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
000001d0 00 fd 2c fa 02 76 63 63 5f 65 6e 63 61 70 73 31 |..,..vcc_encaps1|
000001e0 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
000001f0 00 fd 2b fa 02 76 63 63 5f 65 6e 63 61 70 73 32 |..+..vcc_encaps2|
00000200 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
00000210 00 fd 2a fa 02 76 63 63 5f 65 6e 63 61 70 73 33 |..*..vcc_encaps3|
00000220 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
00000230 00 fd 29 fa 02 76 63 63 5f 65 6e 63 61 70 73 34 |..)..vcc_encaps4|
00000240 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
00000250 00 fd 28 fa 02 76 63 63 5f 65 6e 63 61 70 73 35 |..(..vcc_encaps5|
00000260 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
00000270 00 fd 27 fa 02 76 63 63 5f 65 6e 63 61 70 73 36 |..'..vcc_encaps6|
00000280 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
00000290 00 fd 26 fa 02 76 63 63 5f 65 6e 63 61 70 73 37 |..&..vcc_encaps7|
000002a0 00 30 2e 30 00 ff ff ff ff ff ff ff ff ff ff ff |.0.0............|
000002b0 00 fd 93 fa 02 6d 6f 64 75 6c 61 74 69 6f 6e 00 |.....modulation.|
000002c0 31 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff |1...............|
000002d0 01 ff 33 fd 01 32 31 31 39 36 38 30 30 30 00 ff |..3..211968000..|
000002e0 26 ff 0e fd 01 32 31 31 39 36 38 30 30 30 00 ff |&....211968000..|
000002f0 1c ff 18 fd 01 31 30 35 39 38 34 30 30 30 00 ff |.....105984000..|
00000300 07 ff f7 fb 01 6d 3a 66 3a 22 6d 74 64 31 22 00 |.....m:f:"mtd1".|
00000310 00 fd 97 fa 02 75 73 62 5f 76 69 64 00 30 78 31 |.....usb_vid.0x1|
00000320 36 36 38 00 ff ff ff ff ff ff ff ff ff ff ff ff |668.............|
00000330 00 fd ab fa 02 75 73 62 5f 70 69 64 00 30 78 36 |.....usb_pid.0x6|
00000340 30 31 30 00 ff ff ff ff ff ff ff ff ff ff ff ff |010.............|
00000350 00 fd 84 fa 02 50 72 6f 64 75 63 74 49 44 00 4d |.....ProductID.M|
00000360 31 30 30 30 00 ff ff ff ff ff ff ff ff ff ff ff |1000............|
00000370 00 fd 9f fa 02 48 57 52 65 76 69 73 69 6f 6e 00 |.....HWRevision.|
00000380 32 41 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |2A..............|
00000390 00 fd 7d f8 02 44 53 4c 5f 50 48 59 5f 43 4e 54 |..}..DSL_PHY_CNT|
000003a0 4c 5f 30 00 30 78 30 30 31 30 30 38 30 30 00 ff |L_0.0x00100800..|
000003b0 00 fd a9 fb 01 64 65 66 61 75 6c 74 73 00 00 ff |.....defaults...|
000003c0 08 ff 69 fb 02 30 30 3a 31 35 3a 30 35 3a 41 32 |..i..00:15:05:A2|
000003d0 3a 32 34 3a 33 34 00 ff ff ff ff ff ff ff ff ff |:24:34..........|
000003e0 00 fd 27 f8 03 57 4c 41 4e 5f 48 57 41 44 44 52 |..'..WLAN_HWADDR|
000003f0 00 30 30 3a 31 35 3a 30 35 3a 41 32 3a 32 34 3a |.00:15:05:A2:24:|
00000400 33 34 00 ff ff ff ff ff ff ff ff ff ff ff ff ff |34..............|
00000410 0b ff 65 fb 02 30 30 3a 31 35 3a 30 35 3a 41 32 |..e..00:15:05:A2|
00000420 3a 32 34 3a 33 35 00 ff ff ff ff ff ff ff ff ff |:24:35..........|
00000430 0a ff 65 fb 02 30 30 3a 31 35 3a 30 35 3a 41 32 |..e..00:15:05:A2|
00000440 3a 32 34 3a 33 36 00 ff ff ff ff ff ff ff ff ff |:24:36..........|
00000450 18 ff 56 fb 02 30 30 3a 31 35 3a 30 35 3a 41 32 |..V..00:15:05:A2|
00000460 3a 32 34 3a 33 37 00 ff ff ff ff ff ff ff ff ff |:24:37..........|
00000470 00 fd 70 fa 02 63 6f 6e 6e 65 63 74 69 6f 6e 30 |..p..connection0|

Changed 8 years ago by Michael J Evans <mjevans1983@…>

m1000 env block from 0x0 to 0x480 (offset starts at 128K in to flash)

comment:7 Changed 8 years ago by florian

Seems like checking for the AEIBootVersion set to psbl should be enough to determine if the UPF_AUTOCONF flag should be applied, I will cook up a patch for this.

comment:8 Changed 8 years ago by Michael Evans <mjevans1983@…>

There is also one other complication: on my m1000 unit the bootloader takes up the first 128K of the device, (the initial smaller page area plus the first 64k flash block) and the config-strings are in the 128k to 192k range. Additionally I had to apply another patch to force recognition and use of any base-compliant CFI chip as opposed to only supporting known models. Without that other patch it says the entire chip is a non-programmable 8MByte range.

Changed 8 years ago by florian

Attempt to detect a PSBL bootloader and set the right UART flags accordingly.

comment:9 Changed 8 years ago by florian

Michael, can you try the patch attached and see if that helps? One should also be able to simply do a:

char *psbl;

psbl = prom_getenv("(psbl)");
if (psbl)
   /* Then do PSBL specific stuff */

comment:10 Changed 8 years ago by florian

Ping?

comment:11 Changed 8 years ago by Michael J Evans <mjevans1983@…>

Sorry, I was busy focusing on other things. Thank you for the ping.

I just finished resyncing to the latest SVN version, I'm trying to get a clean build, apply your patch, and then rebuild.

Changed 8 years ago by Michael J Evans <mjevans1983@…>

M1000 serial console patch - updated + reworked

comment:12 Changed 8 years ago by Michael J Evans <mjevans1983@…>

The patch works, but I don't know how to structure it and get it auto-applied within the OpenWRT framework.

The verbosity level is quite low by default, so it's difficult to tell it works due to other bugs.

serial8250: ttyS0 at I/O 0x0 (irq = 15) is a 16550A
console [ttyS0] enabled, bootconsole disabled

The second line is printed when this patch is added, but not before this patch is added.

This leaves me with the bug in the CFI code which ignores chips that lack an extended section but still conform to the baseline CFI specification. Better poke that next...

comment:13 Changed 8 years ago by Michael J Evans <mjevans1983@…>

Nevermind, it's not quite good enough or I'm running at the wrong serial rate. Will update as I get more data.

comment:14 Changed 8 years ago by Michael J Evans <mjevans1983@…>

I've isolated the problem to this:

If setting 0x03 it works (This is what the board boots with).
If setting 0x93 it dies.
If setting 0x13 it works.

include/linux/serial_reg.h :: #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */

Why is this set by default (is nearly always part of standard uart hardware?) and why isn't there a better way of disabling it?

8250.c : static void serial8250_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)

	if (up->capabilities & UART_NATSEMI) {
		/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
		serial_outp(up, UART_LCR, 0xe0);
	} else {
		printk(KERN_INFO "serial8250_set_termios: set UART_LCR + _DLAB (div latch access bit) = %x VS %x , so skipping DLAB\n\n", cval | UART_LCR_DLAB, serial_inp(up, UART_LCR));
		serial_outp(up, UART_LCR, cval /* | UART_LCR_DLAB */);/* set DLAB */
	}

the Qwest Actiontec M1000 has the UAR_LCR set to 0x3 but the existing code wants to set it to 0x93 (0x80 for the UART_LCR_DLAB, and 0x10 for EVEN parity...)

	printk(KERN_INFO "serial8250_set_termios: PATCHED ERROR, If Parity isn't set, why set a PARITY option?\n");
	if (termios->c_cflag & PARENB)
		cval |= UART_LCR_PARITY;
	if (!(termios->c_cflag & PARODD))
		cval |= UART_LCR_EPAR;
#ifdef CMSPAR
	if (termios->c_cflag & CMSPAR)
		cval |= UART_LCR_SPAR;
#endif

comment:15 Changed 8 years ago by Michael Evans <mjevans1983@…>

http://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming#UART_Registers

Ok, so here's what the code looked like before my added printk debug lines.

	if (up->capabilities & UART_NATSEMI) {
		/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
		serial_outp(up, UART_LCR, 0xe0);
	} else {
		serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
	}

	serial_dl_write(up, quot);

	/*
	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
	 * is written without DLAB set, this mode will be disabled.
	 */
	if (up->port.type == PORT_16750)
		serial_outp(up, UART_FCR, fcr);

	serial_outp(up, UART_LCR, cval);		/* reset DLAB */
	up->lcr = cval;					/* Save LCR */

The section of interest is actually denoted by all the LCR and DLAB lines, though the comments are so poor as to be useless for anyone who doesn't know the 8250; which thanks to the first link I now know just enough more about to understand the comments.

There are actually 3 sets of things happening:

  • 1) An exception for a National Semiconductor chip.
  • 2) Writing the divisor for the serial master bitrate rate-clock.
  • 3) A special privileged mode write to a sort of banked version of the FIFO Control Register that sets up an additional mode which is clears for any non-privileged writes to the same register. (It's got a HUGE blob of text explaining it well.)

The noise of # 1 and # 3 distracted me from # 2 happening.

So now I know what to check; the divisor's value...

comment:16 Changed 8 years ago by Michael J Evans <mjevans1983@…>

As suspected, the quot value is wrong. Surprisingly though, it's actually worse; capturing the quot val was easiest if I over-wrote the /new/ calculated value with the /new/ recalled 'boot' value. Things still turned to garbage with the read and re-written value.

Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250: ttyS0 at MMIO 0x8610e00 (irq = 15) is a 16550A
serial8250_console_setup: calling uart_parse_options: result 9600n(6e)8n(6e)
serial8250_set_termios: baud 9600 / quot 407 :: cval 13
serial8250_set_termios: quot = 407 VS
serial8250_set_termios: boot = 345
--- It turns to garbage on the serial console here, but dmesg gets the rest ---
serial8250_set_termios: serial_dl_write quot
console [ttyS0] enabled, bootconsole disabled
physmap platform flash device: 00800000 at 10000000

This calls for some more drastic measures.

comment:17 Changed 8 years ago by Michael J Evans <mjevans1983@…>

I realized that I was trying to print (over the lower serial register) during the critical section. Now reading and writing works. However there's still a rather annoying issue relating to the calculated rate. The clock's don't match up. I'll had to annoyingly collect more data.

  Port	'quot'	'clock'
   300	, no	thanks
  1200	2760	3312000
  4800	 690	3312000
  9600	 345	3312000
 19200	 173	3321600 == 172.5
 38400	  86	3302400 ==  86.25
 57600	  58	3340800 ==  57.5
115200	  29	3340800 ==  28.75

serial8250_set_termios: baud 115200 / quot 34 :: cval 13

Tracing the origin of 34...

uart_get_divisor()
		quot = (port->uartclk + (8 * baud)) / (16 * baud);
quot * (16 * baud) - (8 * baud)= port->uartclk
8 * (quot * 2 * baud - baud) = port->uartclk

Plug in some numbers...
8 * (2760 * 2 * 1200 - 1200) = 52,982,400
Which had previously been...
	uart_port[0].uartclk = ar7_bus_freq() / 2;
105,964,800

In order...

ar7_register_devices: serial type psbl (Qwest Actiontec m1000) detected.  << this is where the above line of code runs.

Clocks: Sync 2:1 mode
Clocks: Setting CPU clock
Adjusted requested frequency 211000000 to 211968000
Clocks: prediv: 1, postdiv: 1, mul: 6
Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
Clocks: Setting DSP clock
Clocks: prediv: 1, postdiv: 1, mul: 5
Clocks: base = 25000000, frequency = 105984000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
Clocks: Setting USB clock
Adjusted requested frequency 48000000 to 47863741
Clocks: prediv: 1, postdiv: 31, mul: 14
Clocks: base = 105984000, frequency = 48000000, prediv = 1, postdiv = 31, postdiv2 = -1, mul = 14

That last one... 52,992,000 produces 2759 at 1200 baud; very very close.  Off by only one from what was set.

29.25, 58.05, 86.75, 173, 345.5, 690.5, 2,760.5

Following the reference equation and using integer math (truncating the results) the numbers match.

ar7_register_devices: serial type psbl (Qwest Actiontec m1000) detected. Using serial clock 52,992,000 not 62500000.

So, I can patch it with a device-specific magic number, but where is that 125,000,000 hz coming from? The function returns an external number, which happens to be quite wrong. It's much too late for me to continue tracking this tonight.

comment:18 Changed 8 years ago by florian

I still do not get why you can't use the original patch which sets the UPF_AUTOCONF flag while registering the UART. Is there anything wrong with this approach?

comment:19 follow-up: Changed 8 years ago by florian

The 125Mhz value is the bus clock, unless your device is being underclocked, which I do not think so, you should probably round up the clock value to something working.

comment:20 Changed 8 years ago by Michael J Evans <mjevans1983@…>

I tried it again in 2.6.32 and it either no longer has the same effect, or months ago I wasn't careful enough when inserting my debugging alterations. I couldn't get a clean compile so I tossed the entire repository and pulled a fresh completely clean copy to make sure I hadn't accidentally gotten something stuck.

I've performed a /vast/ number of bisections using debugging statements and collected enough sample-data to reconstruct the clock-rate my device appears to actually be operating at. The question then what rate is that bus-clock running at; the question is: Why isn't the function returning the actual value of the clock, and should the bus rate somehow be shifted to the standard clock or is the returned value wrong for some reason?

It's ar7_vbus_freq on my device?

Here's a full dump with all of the added debugging statements:

Oh, and the Watchdog timer appears to be using the same source clock:: ar7_wdt: timer margin 59 seconds (prescale 65535, change 48480, freq 52992000)

From the same platform.c function that everything is happening in...

	case AR7_CHIP_7200:
		ar7_wdt_res.start = AR7_REGS_WDT;
	ar7_wdt_res.end = ar7_wdt_res.start + 0x20;

static void ar7_wdt_update_margin(int new_margin)
{
	u32 change;

	change = new_margin * (ar7_vbus_freq() / prescale_value);
	if (change < 1)
		change = 1;
	if (change > 0xffff)
		change = 0xffff;
	ar7_wdt_change(change);
	margin = change * prescale_value / ar7_vbus_freq();
	printk(KERN_INFO DRVNAME
	       ": timer margin %d seconds (prescale %d, change %d, freq %d)\n",
	       margin, prescale_value, change, ar7_vbus_freq());
}

Linux version 2.6.32.12 (aeon@mainline) (gcc version 4.3.3 (GCC) ) #34 Thu May 6 14:06:14 PDT 2010
printk: register console: top: name early
printk: register console: test for CON_BOOT: 0
printk: register console: 
printk: register console: test early_setup: 0
printk: register console: preferred_console test -1
printk: register console: kcmdline tests
printk: register console: tests complete.
printk: register console: do we mask out printbuffer?
printk: register console: test if printbuffer is still set
printk: register console: prep for unregister
bootconsole [early0] enabled
CPU revision is: 00018448 (MIPS 4KEc)
TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x11
Determined physical RAM map:
 memory: 01000000 @ 14000000 (usable)
Initrd not found or empty - disabling initrd
Zone PFN ranges:
  Normal   0x00014000 -> 0x00015000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0: 0x00014000 -> 0x00015000
On node 0 totalpages: 4096
free_area_init_node: node 0, pgdat 94368bd0, node_mem_map 943a3000
  Normal zone: 32 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 4064 pages, LIFO batch:0
Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 4064
Kernel command line: rootfstype=squashfs,jffs2 console=ttyS0,115200n8
PID hash table entries: 64 (order: -4, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Primary instruction cache 16kB, VIPT, 4-way, linesize 16 bytes.
Primary data cache 8kB, 4-way, VIPT, no aliases, linesize 16 bytes
Memory: 12516k/16384k available (2126k kernel code, 3868k reserved, 341k data, 132k init, 0k highmem)
Hierarchical RCU implementation.
NR_IRQS:256
printk: register console: top: name ttyS
printk: register console: test for CON_BOOT: 1
printk: register console: 
printk: register console: test early_setup: -1809538976
printk: register console: preferred_console test 0
printk: register console: kcmdline tests
printk: register console: kcmdline eval 0 : ttyS == ttyS to continue
printk: register console: if 94377c44 is not a null pointer run it with: newcon, "115200n8"
serial8250_console_setup: name ttyS, 115200n8
printk: register console: tests complete.
Calibrating delay loop... 149.50 BogoMIPS (lpj=747520)
Mount-cache hash table entries: 512
NET: Registered protocol family 16
ar7_register_devices: serial type psbl (Qwest Actiontec m1000) detected. Using serial clock 52,992,000 not 62500000.
Clocks: Sync 2:1 mode
Clocks: Setting CPU clock
Adjusted requested frequency 211000000 to 211968000
Clocks: prediv: 1, postdiv: 1, mul: 6
Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
Clocks: Setting DSP clock
Clocks: prediv: 1, postdiv: 1, mul: 5
Clocks: base = 25000000, frequency = 105984000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
Clocks: Setting USB clock
Adjusted requested frequency 48000000 to 47863741
Clocks: prediv: 1, postdiv: 31, mul: 14
Clocks: base = 105984000, frequency = 48000000, prediv = 1, postdiv = 31, postdiv2 = -1, mul = 14
bio: create slab <bio-0> at 0
Switching to clocksource MIPS
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
NET: Registered protocol family 1
squashfs: version 4.0 (2009/01/31) Phillip Lougher
Registering mini_fo version $Id$
JFFS2 version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
msgmni has been set to 24
io scheduler noop registered
io scheduler deadline registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
Serial: DEBUG-TRACE: sparc test.
Serial: DEBUG-TRACE: ret test.
Serial: DEBUG-TRACE: isa test.
Serial: DEBUG-TRACE: add isa.
Serial: DEBUG-TRACE: register isa.
Serial: DEBUG-TRACE: register port 0 has type 3.
Serial: DEBUG-TRACE: register port 1 has type 0.
Serial: DEBUG-TRACE: register ports isa init.
Serial: DEBUG-TRACE: register ports uart add one.
uart_add_one_port: postlocks
uart_add_one_port: configure
uart_configure_port: run
uart_configure_port: type_unk test
uart_configure_port: unk report
serial8250: ttyS0 at MMIO 0x8610e00 (irq = 15) is a 16550A
uart_configure_port: unk power up
uart_configure_port: unk ctrl-deactv
serial8250_set_mctrl: mctrl 0
serial8250_set_mctrl: mcr 0
serial8250_set_mctrl: out
uart_configure_port: re-register console
printk: register console: top: name ttyS
printk: register console: test for CON_BOOT: 1
printk: register console: 
printk: register console: test early_setup: -1809538976
printk: register console: preferred_console test 0
printk: register console: kcmdline tests
printk: register console: kcmdline eval 0 : ttyS == ttyS to continue
printk: register console: if 94377c44 is not a null pointer run it with: newcon, "115200n8"
serial8250_console_setup: name ttyS, 115200n8
serial8250_console_setup: calling uart_parse_options: result 115200n(6e)8n(6e)
uart_set_options: name ttyS
uart_set_options: set_termios
serial8250_set_termios:
serial8250_set_termios: PATCHED ERROR, If Parity isn't set, why set PARODD?
serial8250_set_termios: baud 115200 / quot 29 :: cval 13
serial8250_set_termios: quot off by one 'UART_BUG_QUOT' workaround.
serial8250_set_termios: uart update timeout
serial8250_set_termios: CTS tests
serial8250_set_termios: CTS test MSI 1, result 0
serial8250_set_termios: CTS test UUE/RTOIE 0 then IER out 0
serial8250_set_termios: CTS test CAP_EFR = 0
serial8250_set_termios: beginning probe quot = 29 VS

serial8250_set_termios: probe dump
        DLAB 0  DLAB 1
0       0       1d
1       0       0
2       c1      c1
3       3       83
4       0       0
5       0       0
6       0       0
7       0       0
serial8250_set_termios: PORT_16750? 0 fcr = 0

                                                                
serial8250_set_termios: fcr test 0
serial8250_set_termios: mctrl
serial8250_set_mctrl: mctrl 2
serial8250_set_mctrl: mcr 1
serial8250_set_mctrl: out
serial8250_set_termios: if 1c200 then tty_termios_encode_baud_rate
uart_set_options: name ttyS :: out
printk: register console: set CON_ENABLED
printk: register console: test for selected console and set CON_CONSDEV if yes
printk: register console: tests complete.
printk: register console: do we mask out printbuffer?
printk: register console: test if printbuffer is still set
printk: register console: prep for unregister
console [ttyS0] enabled, bootconsole disabled
uart_configure_port: power down unless /the/ console
uart_configure_port: out
uart_add_one_port: register device
uart_add_one_port: remove UPF_DEAD.
uart_add_one_port: out
Serial: DEBUG-TRACE: register ports uart add one.
uart_add_one_port: postlocks
uart_add_one_port: configure
uart_add_one_port: register device
uart_add_one_port: remove UPF_DEAD.
uart_add_one_port: out
Serial: DEBUG-TRACE: register ports done.
Serial: DEBUG-TRACE: register2 isa.
Serial: DEBUG-TRACE: out.
physmap platform flash device: 00800000 at 10000000
Number of erase regions: 2
Primary Vendor Command Set: 0002 (AMD/Fujitsu Standard)
Primary Algorithm Table at 0040
Alternative Vendor Command Set: 0000 (None)
No Alternate Algorithm Table
Vcc Minimum:  2.7 V
Vcc Maximum:  3.6 V
No Vpp line
Typical byte/word write timeout: 16 µs
Maximum byte/word write timeout: 512 µs
Full buffer write not supported
Typical block erase timeout: 1024 ms
Maximum block erase timeout: 16384 ms
Chip erase not supported
Device size: 0x800000 bytes (8 MiB)
Flash Device Interface description: 0x0002
  - supports x8 and x16 via BYTE# with asynchronous interface
Max. bytes in buffer write: 0x1
Number of Erase Block Regions: 2
  Erase Region #0: BlockSize 0x2000 bytes, 8 blocks
  Erase Region #1: BlockSize 0x10000 bytes, 127 blocks
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
 Amd/Fujitsu Extended Query Table at 0x0040
  WARNING: Unknown Amd/Fujitsu Extended Query vendor:   ec version 0.0. If defaults fail look up the chip.
  Silicon revision: 0
  Address sensitive unlock: Required
  Erase Suspend: Read/write
  Block protection: 1 sectors per group
  Temporary block unprotect: Supported
  Block protect/unprotect scheme: 4
  Number of simultaneous operations: 96
  Burst mode: Not supported
  Page mode: Not supported
  Vpp Supply Minimum Program/Erase Voltage: 8.5 V
  Vpp Supply Maximum Program/Erase Voltage: 12.5 V
  Top/Bottom Boot Block: Bottom boot
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
cmdlinepart partition parsing not available
RedBoot partition parsing not available
4 ar7part partitions found on MTD device physmap-flash.0
Creating 4 MTD partitions on "physmap-flash.0":
0x000000000000-0x000000010000 : "loader"
0x000000020000-0x000000030000 : "config"
0x000000030000-0x000000800000 : "linux"
0x000000100000-0x000000800000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
mtd: partition "rootfs_data" created automatically, ofs=220000, len=5E0000 
0x000000220000-0x000000800000 : "rootfs_data"
Fixed MDIO Bus: probed
cpmac-mii: probed
cpmac: device eth0 (regs: 08610000, irq: 27, phy: 1:1f, mac: 00:15:05:a2:00:00)
ar7_wdt: disabling watchdog timer
ar7_wdt: timer margin 59 seconds (prescale 65535, change 48480, freq 52992000)
Registered led device: status
vlynq0: regs 0x08611800, irq 29, mem 0x04000000
TCP westwood registered
NET: Registered protocol family 17
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (squashfs filesystem) readonly on device 31:3.
Freeing unused kernel memory: 132k freed
Please be patient, while OpenWrt loads ...
serial8250_set_mctrl: mctrl 4002
serial8250_set_mctrl: mcr 9
serial8250_set_mctrl: out
serial8250_set_termios:
serial8250_set_termios: PATCHED ERROR, If Parity isn't set, why set PARODD?
serial8250_set_termios: baud 115200 / quot 29 :: cval 13
serial8250_set_termios: quot off by one 'UART_BUG_QUOT' workaround.
serial8250_set_termios: uart update timeout
serial8250_set_termios: CTS tests
serial8250_set_termios: CTS test MSI 1, result 0
serial8250_set_termios: CTS test UUE/RTOIE 0 then IER out 5
serial8250_set_termios: CTS test CAP_EFR = 0
serial8250_set_termios: beginning probe quot = 29 VS

serial8250_set_termios: probe dump
        DLAB 0  DLAB 1
0       0       1d
1       5       0
2       1       1
3       3       83
4       9       9
5       60      60
6       0       0
7       0       0
serial8250_set_termios: PORT_16750? 0 fcr = 0

                                                                
serial8250_set_termios: fcr test 0
serial8250_set_termios: mctrl
serial8250_set_mctrl: mctrl 4002
serial8250_set_mctrl: mcr 9
serial8250_set_mctrl: out
serial8250_set_termios: if 1c200 then tty_termios_encode_baud_rate
serial8250_set_mctrl: mctrl 4006
serial8250_set_mctrl: mcr b
serial8250_set_mctrl: out
serial8250_set_mctrl: mctrl 4000
serial8250_set_mctrl: mcr 8
serial8250_set_mctrl: out
serial8250_set_mctrl: mctrl 0
serial8250_set_mctrl: mcr 0
serial8250_set_mctrl: out
serial8250_set_mctrl: mctrl 4000
serial8250_set_mctrl: mcr 8
serial8250_set_mctrl: out
serial8250_set_termios:
serial8250_set_termios: PATCHED ERROR, If Parity isn't set, why set PARODD?
serial8250_set_termios: baud 115200 / quot 29 :: cval 13
serial8250_set_termios: quot off by one 'UART_BUG_QUOT' workaround.
serial8250_set_termios: uart update timeout
serial8250_set_termios: CTS tests
serial8250_set_termios: CTS test MSI 1, result 0
serial8250_set_termios: CTS test UUE/RTOIE 0 then IER out 5
serial8250_set_termios: CTS test CAP_EFR = 0
serial8250_set_termios: beginning probe quot = 29 VS

serial8250_set_termios: probe dump
        DLAB 0  DLAB 1
0       0       1d
1       5       0
2       1       1
3       3       83
4       8       8
5       60      60
6       0       0
7       0       0
serial8250_set_termios: PORT_16750? 0 fcr = 0

                                                                
serial8250_set_termios: fcr test 0
serial8250_set_termios: mctrl
serial8250_set_mctrl: mctrl 4000
serial8250_set_mctrl: mcr 8
serial8250_set_mctrl: out
serial8250_set_termios: if 1c200 then tty_termios_encode_baud_rate
serial8250_set_mctrl: mctrl 4006
serial8250_set_mctrl: mcr b
serial8250_set_mctrl: out
mini_fo: using base directory: /
mini_fo: using storage directory: /tmp/root
PHY: 1:1f - Link is Up - 100/Full
device eth0 entered promiscuous mode
br-lan: port 1(eth0) entering forwarding state
NET: Registered protocol family 8
NET: Registered protocol family 20
PPP generic driver version 2.4.2
ip_tables: (C) 2000-2006 Netfilter Core Team
NET: Registered protocol family 24
nf_conntrack version 0.5.0 (197 buckets, 788 max)
registered device TI Avalanche SAR
Ohio250(7200/7100A2) detected
requesting firmware image "ar0700xx.bin"
 avsar: firmware: requesting ar0700xx.bin
avsar firmware released
tn7dsl_set_modulation : Setting mode to 0x1
Creating new root folder avalanche in the proc for the driver stats 
Texas Instruments ATM driver: version:[7.03.01.00]
jffs2_scan_eraseblock(): End of filesystem marker found at 0x0
jffs2_build_filesystem(): unlocking the mtd device... done.
jffs2_build_filesystem(): erasing all blocks after the end marker... done.
mini_fo: using base directory: /
mini_fo: using storage directory: /overlay
ar7_wdt: enabling watchdog timer
ar7_wdt: timer margin 59 seconds (prescale 65535, change 48480, freq 52992000)

comment:21 Changed 8 years ago by Michael Evans <mjevans1983@…>

Ok, so...

build_dir/linux-ar7/linux-2.6.32.12/arch/mips/include/asm/mach-ar7/ar7.h lines 143-

static inline int ar7_bus_freq(void)
{
        return ar7_bus_clock;
}

static inline int ar7_vbus_freq(void)
{
        return ar7_bus_clock / 2;
}
#define ar7_cpmac_freq ar7_vbus_freq

extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;

build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/clock.c

static void __init tnetd7300_init_clocks(void)
{
        ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
                &clocks->bus, bootcr, AR7_AFE_CLOCK);
}
static void __init tnetd7200_init_clocks(void)
{
        if (*bootcr & BOOT_PLL_ASYNC_MODE) {
                ar7_bus_clock =
                        ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
                tnetd7200_set_clock(dsp_base, &clocks->dsp,
                        dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
                        ar7_bus_clock);
        } else
                if (*bootcr & BOOT_PLL_2TO1_MODE) {
                        ar7_bus_clock = ar7_cpu_clock / 2;
                        tnetd7200_set_clock(dsp_base, &clocks->dsp,
                                dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
                                dsp_mul * 2, ar7_bus_clock);
                } else {
                        ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
                                                                / dsp_postdiv;
                        tnetd7200_set_clock(dsp_base, &clocks->dsp,
                                dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
                                dsp_mul * 2, ar7_bus_clock);

It looks like the problem may be that the platform.c is asking for the clock information too early, before the clock driver has had a chance to adjust it.

comment:22 Changed 8 years ago by Michael J Evans <mjevans1983@…>

I now have a patch that works, it's elegantly simple too. I just don't know how to format it to be automatically applied...

commit f9470c6075c9899ec2c183ee913ff380c03cf9d9
Author: Micahel J. Evans <mjevans1983@gmail.com>
Date:   Thu May 6 19:01:00 2010 -0700

    clock init now a core not arch priority event, add clock output message to platform.c

diff --git a/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/clock.c b/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/clock.c
index cc65c8e..a7672db 100644
--- a/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/clock.c
+++ b/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/clock.c
@@ -424,4 +424,4 @@ int __init ar7_init_clocks(void)
 
        return 0;
 }
-arch_initcall(ar7_init_clocks);
+core_initcall(ar7_init_clocks);
diff --git a/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/platform.c b/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/platform.c
index 9691a3e..2c6019c 100644
--- a/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/platform.c
+++ b/trunk/build_dir/linux-ar7/linux-2.6.32.12/arch/mips/ar7/platform.c
@@ -665,6 +665,9 @@ static int __init ar7_register_devices(void)
 #ifdef CONFIG_SERIAL_8250
        static struct uart_port uart_port[2];
 
+       printk (KERN_INFO "ar7_register_devices: serial clock %d hz.\n",
+               ar7_bus_freq() / 2);
+               
        memset(uart_port, 0, sizeof(struct uart_port) * 2);
 
        uart_port[0].type = PORT_16550A;
Linux version 2.6.32.12 (aeon@mainline) (gcc version 4.3.3 (GCC) ) #2 Thu May 6 19:04:36 PDT 2010
bootconsole [early0] enabled
CPU revision is: 00018448 (MIPS 4KEc)
TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x11
Determined physical RAM map:
 memory: 01000000 @ 14000000 (usable)
Initrd not found or empty - disabling initrd
Zone PFN ranges:
  Normal   0x00014000 -> 0x00015000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0: 0x00014000 -> 0x00015000
Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 4064
Kernel command line: rootfstype=squashfs,jffs2 console=ttyS0,115200n8
PID hash table entries: 64 (order: -4, 256 bytes)
Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
Primary instruction cache 16kB, VIPT, 4-way, linesize 16 bytes.
Primary data cache 8kB, 4-way, VIPT, no aliases, linesize 16 bytes
Memory: 12524k/16384k available (2123k kernel code, 3860k reserved, 336k data, 132k init, 0k highmem)
Hierarchical RCU implementation.
NR_IRQS:256
Calibrating delay loop... 149.50 BogoMIPS (lpj=747520)
Mount-cache hash table entries: 512
Clocks: Sync 2:1 mode
Clocks: Setting CPU clock
Adjusted requested frequency 211000000 to 211968000
Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
Clocks: Setting DSP clock
Clocks: base = 25000000, frequency = 105984000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
Clocks: Setting USB clock
Adjusted requested frequency 48000000 to 47863741
Clocks: base = 105984000, frequency = 48000000, prediv = 1, postdiv = 31, postdiv2 = -1, mul = 14
NET: Registered protocol family 16
ar7_register_devices: serial clock 52992000 hz.
bio: create slab <bio-0> at 0
Switching to clocksource MIPS
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 512 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 512 bind 512)
TCP reno registered
NET: Registered protocol family 1
squashfs: version 4.0 (2009/01/31) Phillip Lougher
Registering mini_fo version $Id$
JFFS2 version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
msgmni has been set to 24
io scheduler noop registered
io scheduler deadline registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250: ttyS0 at MMIO 0x8610e00 (irq = 15) is a 16550A
console [ttyS0] enabled, bootconsole disabled
console [ttyS0] enabled, bootconsole disabled
                                             physmap platform flash device: 00800000 at 10000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
 Amd/Fujitsu Extended Query Table at 0x0040
  Unknown Amd/Fujitsu Extended Query version 0.0.
gen_probe: No supported Vendor Command Set found
physmap-flash physmap-flash.0: map_probe failed
Fixed MDIO Bus: probed
cpmac-mii: probed
cpmac: device eth0 (regs: 08610000, irq: 27, phy: 1:1f, mac: 00:15:05:a2:00:00)
ar7_wdt: timer margin 59 seconds (prescale 65535, change 48480, freq 52992000)
Registered led device: status
vlynq0: regs 0x08611800, irq 29, mem 0x04000000
TCP westwood registered
NET: Registered protocol family 17
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
All bugs added by David S. Miller <davem@redhat.com>
VFS: Cannot open root device "<NULL>" or unknown-block(0,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
Rebooting in 3 seconds..
Basic POST completed...     Success.
Last reset cause: Software reset (memory controller also reset)

Oh and cleaning out the source like that also killed my CFI patch, I'll have to re-apply it and commit it this time.

Changed 8 years ago by Michael J Evans <mjevans1983@…>

target/linux/ar7/patches-2.6.32/970-clock-init-race-fix.patch

comment:23 in reply to: ↑ 19 Changed 8 years ago by Michael J Evans <mjevans1983@…>

Replying to florian:

The 125Mhz value is the bus clock, unless your device is being underclocked, which I do not think so, you should probably round up the clock value to something working.

Yeah, in replying to your patch I happened to see some numbers line up which confirmed my suspicion that the clock value was different from the one it was fed. The issue turned out to be a race condition where the clock rate was changed after it had been copied.

comment:24 Changed 8 years ago by florian

  • Resolution set to fixed
  • Status changed from accepted to closed

Fixed with r21404, thanks!

comment:25 Changed 4 years ago by jow

  • Milestone changed from Attitude Adjustment 12.09 to Barrier Breaker 14.07

Milestone Attitude Adjustment 12.09 deleted

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