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Opened 10 years ago

Closed 10 years ago

#2329 closed defect (fixed)

Changeset r8423 breaks VYLNQ-PCI linking on DG834G

Reported by: NRForbes Owned by: nico
Priority: normal Milestone:
Component: packages Version:
Keywords: Cc:

Description

Hi,

I am running r8650 on a DG834Gv1 and vlynq-pci never links sucessfully. dmesg shows only this:

vlynq0: regs 0x08611800, irq 29, mem 0x04000000
vlynq1: regs 0x08611c00, irq 33, mem 0x0c000000
VLYNQ: Setting clock to 62500000 (clock divider 4)
VLYNQ: Setting clock to 62500000 (clock divider 4)
registering PCI controller with io_map_base unset

Some debugging of the vlynq_linked() routine in vlynq.c shows that dev->local->status & VLYNQ_STATUS_LINK never becomes true.

The changes applied in changeset r8423 alter the order in which dev->local->control is initialised. For the DG834G at least, VLYNQ_CTRL_CLOCK_INT has to be set at the same time as or after the divider (VLYNQ_CTRL_CLOCK_DIV) is set.

I attached a diff that corrects this. dmesg now shows:

vlynq0: regs 0x08611800, irq 29, mem 0x04000000
vlynq1: regs 0x08611c00, irq 33, mem 0x0c000000
VLYNQ: Setting clock to 62500000 (clock divider 4)
vlynq0: linked
vlynq-pci: attaching device TI ACX111 at vlynq0
VLYNQ: Setting clock to 62500000 (clock divider 4)
registering PCI controller with io_map_base unset

Nick.

Attachments (1)

vlynq_link-fix.diff (658 bytes) - added by NRForbes 10 years ago.
fix for vlynq-pci linking on DG834Gv1

Download all attachments as: .zip

Change History (5)

Changed 10 years ago by NRForbes

fix for vlynq-pci linking on DG834Gv1

comment:1 Changed 10 years ago by nico

  • Owner changed from developers to nico
  • Status changed from new to assigned

comment:2 Changed 10 years ago by NRForbes

The latest set of AR7 changes appear to have resolved this issue (as of r8770).

comment:3 Changed 10 years ago by nabcore

Can this therefore be closed?

comment:4 Changed 10 years ago by ejka

  • Resolution set to fixed
  • Status changed from assigned to closed

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