Modify

Opened 11 years ago

Closed 11 years ago

#1496 closed defect (fixed)

WL500G Premium Support

Reported by: jhansen@… Owned by: nbd
Priority: high Milestone: Kamikaze 7.06
Component: base system Version:
Keywords: wl500g wl500gp time pci Cc:

Description

The following attachments fix the timer bugs, PCI bugs, and add a profile for the WL500G Premium. Have fun!

Attachments (3)

wl500g-profile.patch (563 bytes) - added by jhansen@… 11 years ago.
wl500gp profile
wl500g-ssb_cpuclock.patch (2.4 KB) - added by jhansen@… 11 years ago.
ssb_cpuclock fix. Apply before ssb_pci patch.
wl500g-ssb_pci.patch (1.3 KB) - added by jhansen@… 11 years ago.
ssb_pci fix

Download all attachments as: .zip

Change History (11)

Changed 11 years ago by jhansen@…

wl500gp profile

Changed 11 years ago by jhansen@…

ssb_cpuclock fix. Apply before ssb_pci patch.

Changed 11 years ago by jhansen@…

ssb_pci fix

comment:1 Changed 11 years ago by mbm

The PCI patch is rather ugly and doesn't appear to fix the actual problem.

The bogomips calibration should be done early in init to establish the delay loop. If the PLL is slow to initialize then the bogomips calibration could be thrown, we've seen that problem with the brcm-2.4 releases. See [5435], a simple fix that gives the pll 6 cycles before the bogomips calibration is run.

comment:2 Changed 11 years ago by nbd

  • Owner changed from developers to nbd
  • Status changed from new to assigned

Please try http://nbd.name/pci47xx.patch and see if it replaces the delay hacks in your PCI patch

comment:3 Changed 11 years ago by edo

for me it work with:

  1. wl500g-ssb_cpuclock.patch by jhansen@…
  2. pci47xx.patch by nbd
  3. adding two strings from jhansen's patch to pcicore.c:
    val = SSB_PCICORE_ARBCTL_INTERN;
    pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 
    


ps: wl500gp need uhci, not ohci (chip from via is used).

comment:4 Changed 11 years ago by edo

oops. pci work without pci47xx.patch too.
we need only add two lines to pcicore.c.

but i like this patch (pci47xx.patch) - it don't break anything, only allow right delay calculation.

comment:5 Changed 11 years ago by jhansen@…

That sounds like a good solution. Move the pci init to *after* the delay loop is calibrated, take out all of my ugly delays (but be sure to keep the 300 ms mdelay right before the controller is registered), and do make sure that the SSB_PCICORE_ARBCTL register write is in there, since it is key on the WL500gp.

And replace ohci with uhci and uhci-iv. The timer patch should stay the same (it just pulls in the same timer logic that exists in the 2.4 BSP).

comment:6 Changed 11 years ago by anonymous

That sounds like a good solution. Move the pci init to *after* the delay loop is calibrated, take out all of my ugly delays (but be sure to keep the 300 ms mdelay right before the controller is registered),


it work for me without mdelay(300) (and without udelays too).


and do make sure that the SSB_PCICORE_ARBCTL register write is in there, since it is key on the WL500gp.


is this code compatible with non-asus devices?


And replace ohci with uhci and uhci-iv.


afaik in 2.6 present only one uhci driver

comment:7 Changed 11 years ago by jhansen@…

The ARBVTL write code works fine with the WGT634U (i.e. PCI still works great). I copied those lines from the old 2.4 BSP since PCI wasn't working on the WL500gp without them. The delays are necessary in the 2.4 BSP, but I'm not sure about the new BSP.

comment:8 Changed 11 years ago by nbd

  • Resolution set to fixed
  • Status changed from assigned to closed

fixes added in [6639]. thanks for your work!

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