Changeset 9962


Ignore:
Timestamp:
2007-12-27T15:58:48+01:00 (10 years ago)
Author:
juhosg
Message:

[adm5120] change switch register access macros

Location:
trunk/target/linux/adm5120/files
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c

    r9263 r9962  
    5353        u32     t; 
    5454 
    55         SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); 
    56         SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
     55        SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); 
     56        SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
    5757 
    5858        t = (ns+640) / 640; 
    5959        t &= TIMER_PERIOD_MASK; 
    60         SW_WRITE_REG(TIMER, t | TIMER_TE); 
     60        SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE); 
    6161 
    6262        /* wait until the timer expires */ 
    6363        do { 
    64                 t = SW_READ_REG(TIMER_INT); 
     64                t = SW_READ_REG(SWITCH_REG_TIMER_INT); 
    6565        } while ((t & TIMER_INT_TOS) == 0); 
    6666 
    6767        /* leave the timer disabled */ 
    68         SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); 
    69         SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
     68        SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); 
     69        SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
    7070} 
    7171 
     
    7575        u32 clks; 
    7676 
    77         code = SW_READ_REG(CODE); 
     77        code = SW_READ_REG(SWITCH_REG_CODE); 
    7878 
    7979        adm5120_product_code = CODE_GET_PC(code); 
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/gpio.c

    r9715 r9962  
    344344{ 
    345345        gpio_conf2 |= GPIO_CONF2_CSX0; 
    346         SW_WRITE_REG(GPIO_CONF2, gpio_conf2); 
     346        SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); 
    347347 
    348348        adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID; 
     
    353353{ 
    354354        gpio_conf2 |= GPIO_CONF2_CSX1; 
    355         SW_WRITE_REG(GPIO_CONF2, gpio_conf2); 
     355        SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); 
    356356 
    357357        adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID; 
     
    363363{ 
    364364        gpio_conf2 |= GPIO_CONF2_EW; 
    365         SW_WRITE_REG(GPIO_CONF2, gpio_conf2); 
     365        SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); 
    366366 
    367367        adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID; 
     
    373373 
    374374        gpio_conf2 = 0; 
    375         SW_WRITE_REG(GPIO_CONF2, gpio_conf2); 
     375        SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); 
    376376 
    377377        for (i = 0; i < ADM5120_GPIO_COUNT; i++) 
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/memory.c

    r9263 r9962  
    8383        u8      *p; 
    8484 
    85         memctrl = SW_READ_REG(MEMCTRL); 
     85        memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL); 
    8686        switch (memctrl & MEMCTRL_SDRS_MASK) { 
    8787        case MEMCTRL_SDRS_4M: 
     
    149149                        break; 
    150150                } 
    151                 SW_WRITE_REG(MEMCTRL, memctrl); 
     151                SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl); 
    152152        } 
    153153 
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/reset.c

    r9263 r9962  
    4949                adm5120_board_reset(); 
    5050 
    51         SW_WRITE_REG(SOFT_RESET, 1); 
     51        SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1); 
    5252} 
    5353 
  • trunk/target/linux/adm5120/files/drivers/char/watchdog/adm5120_wdt.c

    r9961 r9962  
    11/* 
    2  *      ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver  
     2 *      ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver 
    33 *      Copyright (c) Ondrej Zajicek <santiago@crfreenet.org>, 2007 
    44 * 
     
    4848{ 
    4949        u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16); 
    50         SW_WRITE_REG(WDOG0, val); 
    51 } 
    52  
    53 /*  
     50        SW_WRITE_REG(SWITCH_REG_WDOG0, val); 
     51} 
     52 
     53/* 
    5454   It looks like WDOG0-register-write don't modify counter, 
    5555   but WDOG0-register-read resets counter. 
     
    5858static inline void wdt_reset_counter(void) 
    5959{ 
    60         SW_READ_REG(WDOG0); 
     60        SW_READ_REG(SWITCH_REG_WDOG0); 
    6161} 
    6262 
    6363static inline void wdt_disable(void) 
    6464{ 
    65         SW_WRITE_REG(WDOG0, 0x7FFF0000); 
    66 } 
    67  
    68  
    69   
     65        SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000); 
     66} 
     67 
     68 
     69 
    7070static int wdt_open(struct inode *inode, struct file *file) 
    7171{ 
  • trunk/target/linux/adm5120/files/drivers/mtd/maps/adm5120-flash.c

    r9496 r9962  
    262262        if (info->amap.window_size == 0) { 
    263263                /* get memory window size */ 
    264                 t = SW_READ_REG(MEMCTRL) >> fdesc->srs_shift; 
     264                t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift; 
    265265                t &= MEMCTRL_SRS_MASK; 
    266266                info->amap.window_size = flash_sizes[t]; 
  • trunk/target/linux/adm5120/files/drivers/net/adm5120sw.c

    r9361 r9962  
    281281        u32 t; 
    282282 
    283         t = SW_READ_REG(PHY_STATUS); 
     283        t = sw_read_reg(SWITCH_REG_PHY_STATUS); 
    284284        SW_DBG("phy_status: %08X\n", t); 
    285285 
    286         t = SW_READ_REG(CPUP_CONF); 
     286        t = sw_read_reg(SWITCH_REG_CPUP_CONF); 
    287287        SW_DBG("cpup_conf: %08X%s%s%s\n", t, 
    288288                (t & CPUP_CONF_DCPUP) ? " DCPUP" : "", 
     
    290290                (t & CPUP_CONF_BTM) ? " BTM" : ""); 
    291291 
    292         t = SW_READ_REG(PORT_CONF0); 
     292        t = sw_read_reg(SWITCH_REG_PORT_CONF0); 
    293293        SW_DBG("port_conf0: %08X\n", t); 
    294         t = SW_READ_REG(PORT_CONF1); 
     294        t = sw_read_reg(SWITCH_REG_PORT_CONF1); 
    295295        SW_DBG("port_conf1: %08X\n", t); 
    296         t = SW_READ_REG(PORT_CONF2); 
     296        t = sw_read_reg(SWITCH_REG_PORT_CONF2); 
    297297        SW_DBG("port_conf2: %08X\n", t); 
    298298 
    299         t = SW_READ_REG(VLAN_G1); 
     299        t = sw_read_reg(SWITCH_REG_VLAN_G1); 
    300300        SW_DBG("vlan g1: %08X\n", t); 
    301         t = SW_READ_REG(VLAN_G2); 
     301        t = sw_read_reg(SWITCH_REG_VLAN_G2); 
    302302        SW_DBG("vlan g2: %08X\n", t); 
    303303 
    304         t = SW_READ_REG(BW_CNTL0); 
     304        t = sw_read_reg(SWITCH_REG_BW_CNTL0); 
    305305        SW_DBG("bw_cntl0: %08X\n", t); 
    306         t = SW_READ_REG(BW_CNTL1); 
     306        t = sw_read_reg(SWITCH_REG_BW_CNTL1); 
    307307        SW_DBG("bw_cntl1: %08X\n", t); 
    308308 
    309         t = SW_READ_REG(PHY_CNTL0); 
     309        t = sw_read_reg(SWITCH_REG_PHY_CNTL0); 
    310310        SW_DBG("phy_cntl0: %08X\n", t); 
    311         t = SW_READ_REG(PHY_CNTL1); 
     311        t = sw_read_reg(SWITCH_REG_PHY_CNTL1); 
    312312        SW_DBG("phy_cntl1: %08X\n", t); 
    313         t = SW_READ_REG(PHY_CNTL2); 
     313        t = sw_read_reg(SWITCH_REG_PHY_CNTL2); 
    314314        SW_DBG("phy_cntl2: %08X\n", t); 
    315         t = SW_READ_REG(PHY_CNTL3); 
     315        t = sw_read_reg(SWITCH_REG_PHY_CNTL3); 
    316316        SW_DBG("phy_cntl3: %08X\n", t); 
    317         t = SW_READ_REG(PHY_CNTL4); 
     317        t = sw_read_reg(SWITCH_REG_PHY_CNTL4); 
    318318        SW_DBG("phy_cntl4: %08X\n", t); 
    319319 
    320         t = SW_READ_REG(INT_STATUS); 
     320        t = sw_read_reg(SWITCH_REG_INT_STATUS); 
    321321        sw_dump_intr_mask("int_status: ", t); 
    322322 
    323         t = SW_READ_REG(INT_MASK); 
     323        t = sw_read_reg(SWITCH_REG_INT_MASK); 
    324324        sw_dump_intr_mask("int_mask: ", t); 
    325325 
    326         t = SW_READ_REG(SHDA); 
     326        t = sw_read_reg(SWITCH_REG_SHDA); 
    327327        SW_DBG("shda: %08X\n", t); 
    328         t = SW_READ_REG(SLDA); 
     328        t = sw_read_reg(SWITCH_REG_SLDA); 
    329329        SW_DBG("slda: %08X\n", t); 
    330         t = SW_READ_REG(RHDA); 
     330        t = sw_read_reg(SWITCH_REG_RHDA); 
    331331        SW_DBG("rhda: %08X\n", t); 
    332         t = SW_READ_REG(RLDA); 
     332        t = sw_read_reg(SWITCH_REG_RLDA); 
    333333        SW_DBG("rlda: %08X\n", t); 
    334334} 
     
    10621062                (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) | 
    10631063                PHY_CNTL2_RMAE; 
    1064         SW_WRITE_REG(PHY_CNTL2, t); 
     1064        sw_write_reg(SWITCH_REG_PHY_CNTL2, t); 
    10651065 
    10661066        t = sw_read_reg(SWITCH_REG_PHY_CNTL3); 
  • trunk/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_nand.h

    r9118 r9962  
    6666static inline void adm5120_nand_enable(void) 
    6767{ 
    68         SW_WRITE_REG(BW_CNTL1, BW_CNTL1_NAND_ENABLE); 
    69         SW_WRITE_REG(BOOT_DONE, 1); 
     68        SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE); 
     69        SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1); 
    7070} 
    7171 
  • trunk/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h

    r9700 r9962  
    3333 
    3434#define SW_READ_REG(r)          __raw_readl( \ 
    35         (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r) 
     35        (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) 
    3636#define SW_WRITE_REG(r, v)      __raw_writel((v), \ 
    37         (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r) 
     37        (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) 
    3838 
    3939/* Switch register offsets */ 
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