Changeset 9279


Ignore:
Timestamp:
2007-10-13T04:04:37+02:00 (10 years ago)
Author:
nbd
Message:

add patches for 2.6.23 on brcm47xx (not enabled yet)

Location:
trunk/target/linux
Files:
12 added
1 deleted
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/brcm47xx/files/arch/mips/bcm947xx/setup.c

    r6563 r9279  
    3232#include <linux/serial_core.h> 
    3333#include <linux/serial_reg.h> 
     34#include <linux/serial_8250.h> 
    3435#include <asm/bootinfo.h> 
    3536#include <asm/time.h> 
     
    108109} 
    109110 
     111static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv) 
     112{ 
     113        char *s; 
     114         
     115        // TODO 
     116        //iv->boardinfo.vendor =  
     117        if ((s = nvram_get("boardtype"))) 
     118                iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0); 
     119        if ((s = nvram_get("boardrev"))) 
     120                iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0); 
     121        bcm47xx_fill_sprom(&iv->sprom); 
     122        return 0; 
     123} 
     124 
    110125void __init plat_mem_setup(void) 
    111126{ 
     
    114129        struct ssb_mipscore *mcore; 
    115130 
    116         err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom); 
     131        err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_get_invariants); 
    117132        if (err) { 
    118133                const char *msg = "Failed to initialize SSB bus (err %d)\n"; 
  • trunk/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c

    r7691 r9279  
    9494        /* Enable PCI bridge BAR1 prefetch and burst */ 
    9595        pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); 
     96 
     97        /* Make sure our latency is high enough to handle the devices behind us */ 
     98        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8); 
    9699} 
    97100DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge); 
    98101 
    99 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 
     102int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 
    100103{ 
    101104        return ssb_mips_irq(extpci_core->dev) + 2; 
     
    111114        if (unlikely(pc->cardbusmode && dev > 1)) 
    112115                goto out; 
    113         if (bus == 0) { 
     116        if (bus == 0) {//FIXME busnumber ok? 
    114117                /* Type 0 transaction */ 
    115118                if (unlikely(dev >= SSB_PCI_SLOT_MAX)) 
     
    225228                break; 
    226229        } 
    227         writel(*((const u32 *)buf), mmio); 
     230        writel(val, mmio); 
    228231 
    229232        err = 0; 
     
    308311        val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ 
    309312        pcicore_write32(pc, SSB_PCICORE_CTL, val); 
     313        val = SSB_PCICORE_ARBCTL_INTERN; 
     314        pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);  
    310315        udelay(1); 
    311316 
     
    337342         * to non-MIPS platform. */ 
    338343        set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000)); 
     344        mdelay(300); 
    339345        register_pci_controller(&ssb_pcicore_controller); 
    340346} 
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