Changeset 8705


Ignore:
Timestamp:
2007-09-09T14:50:32+02:00 (10 years ago)
Author:
juhosg
Message:

[adm5120] cleanup memory detection code, fix #2244

Location:
trunk/target/linux/adm5120/files/arch/mips/adm5120
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c

    r8538 r8705  
    2626#include <linux/init.h> 
    2727 
     28#include <asm/io.h> 
    2829#include <asm/bootinfo.h> 
    2930#include <asm/addrspace.h> 
    3031 
    31 #include <asm/mach-adm5120/adm5120_info.h> 
    32 #include <asm/mach-adm5120/adm5120_defs.h> 
    33 #include <asm/mach-adm5120/adm5120_switch.h> 
     32#include <adm5120_info.h> 
     33#include <adm5120_defs.h> 
     34#include <adm5120_switch.h> 
    3435 
    3536unsigned int adm5120_product_code; 
     
    3839unsigned int adm5120_nand_boot; 
    3940unsigned long adm5120_speed; 
    40  
    41 #define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r)) 
    42 #define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v) 
    4341 
    4442/* 
     
    5553        u32     t; 
    5654 
    57         SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); 
    58         SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
     55        SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); 
     56        SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
    5957 
    6058        t = (ns+640) / 640; 
    6159        t &= TIMER_PERIOD_MASK; 
    62         SWITCH_WRITE(SWITCH_REG_TIMER, t | TIMER_TE); 
     60        SW_WRITE_REG(TIMER, t | TIMER_TE); 
    6361 
    6462        /* wait until the timer expires */ 
    6563        do { 
    66                 t = SWITCH_READ(SWITCH_REG_TIMER_INT); 
     64                t = SW_READ_REG(TIMER_INT); 
    6765        } while ((t & TIMER_INT_TOS) == 0); 
    6866 
    6967        /* leave the timer disabled */ 
    70         SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); 
    71         SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
     68        SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT); 
     69        SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); 
    7270} 
    7371 
     
    7775        u32 clks; 
    7876 
    79         code = SWITCH_READ(SWITCH_REG_CODE); 
     77        code = SW_READ_REG(CODE); 
    8078 
    8179        adm5120_product_code = CODE_GET_PC(code); 
  • trunk/target/linux/adm5120/files/arch/mips/adm5120/memory.c

    r8538 r8705  
    2626#include <linux/kernel.h> 
    2727 
     28#include <asm/io.h> 
    2829#include <asm/bootinfo.h> 
    2930#include <asm/addrspace.h> 
    3031 
    31 #include <asm/mach-adm5120/adm5120_info.h> 
    32 #include <asm/mach-adm5120/adm5120_defs.h> 
    33 #include <asm/mach-adm5120/adm5120_switch.h> 
    34 #include <asm/mach-adm5120/adm5120_mpmc.h> 
    35  
    36 #define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r)) 
    37 #define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v) 
    38  
    39 #define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r)) 
    40 #define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v) 
     32#include <adm5120_info.h> 
     33#include <adm5120_defs.h> 
     34#include <adm5120_switch.h> 
     35#include <adm5120_mpmc.h> 
    4136 
    4237#if 1 
     
    4641#endif 
    4742 
    48 #define MEM_WR_DELAY    10000 /* 0.01 usec */ 
     43unsigned long adm5120_memsize; 
    4944 
    50 unsigned long adm5120_memsize; 
     45#define MEM_READL(a)            __raw_readl((void __iomem *)(a)) 
     46#define MEM_WRITEL(a, v)        __raw_writel((v), (void __iomem *)(a)) 
    5147 
    5248static int __init mem_check_pattern(u8 *addr, unsigned long offs) 
    5349{ 
    54         volatile u32 *p1 = (volatile u32 *)addr; 
    55         volatile u32 *p2 = (volatile u32 *)(addr+offs); 
     50        u32 *p1 = (u32 *)addr; 
     51        u32 *p2 = (u32 *)(addr+offs); 
    5652        u32 t,u,v; 
    57  
    5853        /* save original value */ 
    59         t = *p1; 
    60         u = *p2; 
     54        t = MEM_READL(p1); 
     55        u = MEM_READL(p2); 
    6156 
    6257        if (t != u) 
     
    6964        mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1); 
    7065 
    71         *p1 = v; 
    72         mem_dbg("delay %d ns\n", MEM_WR_DELAY); 
    73         adm5120_ndelay(MEM_WR_DELAY); 
    74         u = *p2; 
     66        MEM_WRITEL(p1, v); 
     67 
     68        /* flush write buffers */ 
     69        MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB); 
     70 
     71        u = MEM_READL(p2); 
    7572 
    7673        mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u); 
    7774 
    7875        /* restore original value */ 
    79         *p1 = t; 
     76        MEM_WRITEL(p1, t); 
    8077 
    8178        return (v == u); 
     
    8885        u8      *p; 
    8986 
    90         memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL); 
     87        memctrl = SW_READ_REG(MEMCTRL); 
    9188        switch (memctrl & MEMCTRL_SDRS_MASK) { 
    9289        case MEMCTRL_SDRS_4M: 
     
    103100                break; 
    104101        } 
    105  
    106         /* disable buffers for both SDRAM banks */ 
    107         mem_dbg("disable buffers for both banks\n"); 
    108         MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE); 
    109         MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE); 
    110102 
    111103        mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20); 
     
    160152                        break; 
    161153                } 
    162                 SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl); 
     154                SW_WRITE_REG(MEMCTRL, memctrl); 
    163155        } 
    164156 
    165157out: 
    166         /* reenable buffer for both SDRAM banks */ 
    167         mem_dbg("enable buffers for both banks\n"); 
    168         MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE); 
    169         MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE); 
    170  
    171158        mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 , 
    172159                size >>20); 
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