Changeset 47842


Ignore:
Timestamp:
2015-12-11T16:03:27+01:00 (2 years ago)
Author:
blogic
Message:

ramips: enable CPS for mt7621

Enables CPS multiprocessing instead ob obsoleted CMP for mt7621.

This patch fixes a few issues currently existing on 4.3 kernel with at least ubnt-erx:

  • iperf shows only 50Mbits on direct gigabit connection to desktop,
  • ping times jump to 5-6ms to dorectly connected desktop
  • /proc/interrupts shows spurious interrups (ERR)

Signed-off-by: Nikolay Martynov <mar.kolya@…>

Location:
trunk/target/linux/ramips
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ramips/dts/mt7621.dtsi

    r47836 r47842  
    238238        gic: interrupt-controller@1fbc0000 { 
    239239                compatible = "mti,gic"; 
    240                 reg = <0x1fbc0000 0x80>; 
     240                reg = <0x1fbc0000 0x2000>; 
    241241 
    242242                interrupt-controller; 
  • trunk/target/linux/ramips/mt7621/config-4.3

    r47831 r47842  
    66CONFIG_ARCH_HAS_RESET_CONTROLLER=y 
    77# CONFIG_ARCH_HAS_SG_CHAIN is not set 
     8CONFIG_ARCH_HIBERNATION_POSSIBLE=y 
    89CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y 
    910CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y 
    1011CONFIG_ARCH_REQUIRE_GPIOLIB=y 
    1112CONFIG_ARCH_SUPPORTS_UPROBES=y 
     13CONFIG_ARCH_SUSPEND_POSSIBLE=y 
    1214CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y 
    1315CONFIG_BOARD_SCACHE=y 
     
    118120CONFIG_MIPS=y 
    119121CONFIG_MIPS_CM=y 
    120 CONFIG_MIPS_CMP=y 
     122CONFIG_MIPS_CPC=y 
     123CONFIG_MIPS_CPS=y 
    121124CONFIG_MIPS_CPU_SCACHE=y 
    122125CONFIG_MIPS_GIC=y 
     
    227230CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 
    228231CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 
     232CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y 
    229233CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 
    230234CONFIG_SYS_SUPPORTS_MIPS16=y 
    231 CONFIG_SYS_SUPPORTS_MIPS_CMP=y 
     235CONFIG_SYS_SUPPORTS_MIPS_CPS=y 
    232236CONFIG_SYS_SUPPORTS_MULTITHREADING=y 
    233237CONFIG_SYS_SUPPORTS_SCHED_SMT=y 
  • trunk/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch

    r47839 r47842  
    121121        prompt "Ralink SoC selection" 
    122122        default SOC_RT305X 
    123 @@ -34,6 +39,15 @@ choice 
     123@@ -34,6 +39,14 @@ choice 
    124124        config SOC_MT7620 
    125125                bool "MT7620/8" 
     
    130130+               select SYS_SUPPORTS_MULTITHREADING 
    131131+               select SYS_SUPPORTS_SMP 
    132 +               select SYS_SUPPORTS_MIPS_CMP 
     132+               select SYS_SUPPORTS_MIPS_CPS 
    133133+               select MIPS_GIC 
    134 +               select IRQ_GIC 
    135134+               select HW_HAS_PCI 
    136135 endchoice 
    137136  
    138137 choice 
    139 @@ -65,6 +79,10 @@ choice 
     138@@ -65,6 +78,10 @@ choice 
    140139                depends on SOC_MT7620 
    141140                select BUILTIN_DTB 
     
    150149--- a/arch/mips/ralink/Makefile 
    151150+++ b/arch/mips/ralink/Makefile 
    152 @@ -6,16 +6,21 @@ 
     151@@ -6,16 +6,20 @@ 
    153152 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 
    154153 # Copyright (C) 2013 John Crispin <blogic@openwrt.org> 
     
    162161  
    163162+obj-$(CONFIG_IRQ_INTC) += irq.o 
    164 +obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o 
    165 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o 
     163+obj-$(CONFIG_MIPS_GIC) += irq-gic.o 
    166164+ 
    167165 obj-$(CONFIG_SOC_RT288X) += rt288x.o 
     
    186184--- /dev/null 
    187185+++ b/arch/mips/ralink/irq-gic.c 
    188 @@ -0,0 +1,42 @@ 
     186@@ -0,0 +1,18 @@ 
    189187+#include <linux/init.h> 
    190 +#include <linux/sched.h> 
    191 +#include <linux/slab.h> 
    192 +#include <linux/interrupt.h> 
    193 +#include <linux/kernel_stat.h> 
    194 +#include <linux/hardirq.h> 
    195 +#include <linux/preempt.h> 
    196 +#include <linux/irqdomain.h> 
    197 +#include <linux/of_platform.h> 
    198 +#include <linux/of_address.h> 
    199 +#include <linux/of_irq.h> 
    200 + 
    201 +#include <asm/irq_cpu.h> 
    202 +#include <asm/mipsregs.h> 
    203 + 
    204 +#include <asm/irq.h> 
    205 +#include <asm/setup.h> 
    206 + 
    207 +#include <asm/mips-cm.h> 
     188+ 
     189+#include <linux/of.h> 
     190+#include <linux/irqchip.h> 
     191+ 
    208192+#include <linux/irqchip/mips-gic.h> 
    209 + 
    210 +#include <asm/mach-ralink/mt7621.h> 
    211 + 
    212 +extern int __init gic_of_init(struct device_node *node, 
    213 +                             struct device_node *parent); 
    214193+ 
    215194+unsigned int get_c0_compare_int(void) 
     
    218197+} 
    219198+ 
    220 +static struct of_device_id __initdata of_irq_ids[] = { 
    221 +       { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, 
    222 +       { .compatible = "mti,gic", .data = gic_of_init }, 
    223 +       {}, 
    224 +}; 
    225 + 
    226199+void __init 
    227200+arch_init_irq(void) 
    228201+{ 
    229 +       of_irq_init(of_irq_ids); 
    230 +} 
    231 --- /dev/null 
    232 +++ b/arch/mips/ralink/malta-amon.c 
    233 @@ -0,0 +1,81 @@ 
    234 +/* 
    235 + * Copyright (C) 2007  MIPS Technologies, Inc. 
    236 + *     All rights reserved. 
    237 + 
    238 + *  This program is free software; you can distribute it and/or modify it 
    239 + *  under the terms of the GNU General Public License (Version 2) as 
    240 + *  published by the Free Software Foundation. 
    241 + * 
    242 + *  This program is distributed in the hope it will be useful, but WITHOUT 
    243 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    244 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
    245 + *  for more details. 
    246 + * 
    247 + *  You should have received a copy of the GNU General Public License along 
    248 + *  with this program; if not, write to the Free Software Foundation, Inc., 
    249 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 
    250 + * 
    251 + * Arbitrary Monitor interface 
    252 + */ 
    253 + 
    254 +#include <linux/kernel.h> 
    255 +#include <linux/init.h> 
    256 +#include <linux/smp.h> 
    257 + 
    258 +#include <asm/addrspace.h> 
    259 +#include <asm/mips-boards/launch.h> 
    260 +#include <asm/mipsmtregs.h> 
    261 + 
    262 +int amon_cpu_avail(int cpu) 
    263 +{ 
    264 +       struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); 
    265 + 
    266 +       if (cpu < 0 || cpu >= NCPULAUNCH) { 
    267 +               pr_debug("avail: cpu%d is out of range\n", cpu); 
    268 +               return 0; 
    269 +       } 
    270 + 
    271 +       launch += cpu; 
    272 +       if (!(launch->flags & LAUNCH_FREADY)) { 
    273 +               pr_debug("avail: cpu%d is not ready\n", cpu); 
    274 +               return 0; 
    275 +       } 
    276 +       if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { 
    277 +               pr_debug("avail: too late.. cpu%d is already gone\n", cpu); 
    278 +               return 0; 
    279 +       } 
    280 + 
    281 +       return 1; 
    282 +} 
    283 + 
    284 +void amon_cpu_start(int cpu, 
    285 +                   unsigned long pc, unsigned long sp, 
    286 +                   unsigned long gp, unsigned long a0) 
    287 +{ 
    288 +       volatile struct cpulaunch *launch = 
    289 +               (struct cpulaunch  *)CKSEG0ADDR(CPULAUNCH); 
    290 + 
    291 +       if (!amon_cpu_avail(cpu)) 
    292 +               return; 
    293 +       if (cpu == smp_processor_id()) { 
    294 +               pr_debug("launch: I am cpu%d!\n", cpu); 
    295 +               return; 
    296 +       } 
    297 +       launch += cpu; 
    298 + 
    299 +       pr_debug("launch: starting cpu%d\n", cpu); 
    300 + 
    301 +       launch->pc = pc; 
    302 +       launch->gp = gp; 
    303 +       launch->sp = sp; 
    304 +       launch->a0 = a0; 
    305 + 
    306 +       smp_wmb();              /* Target must see parameters before go */ 
    307 +       launch->flags |= LAUNCH_FGO; 
    308 +       smp_wmb();              /* Target must see go before we poll  */ 
    309 + 
    310 +       while ((launch->flags & LAUNCH_FGONE) == 0) 
    311 +               ; 
    312 +       smp_rmb();      /* Target will be updating flags soon */ 
    313 +       pr_debug("launch: cpu%d gone!\n", cpu); 
    314 +} 
     202+       irqchip_init(); 
     203+} 
     204+ 
    315205--- /dev/null 
    316206+++ b/arch/mips/ralink/mt7621.c 
    317 @@ -0,0 +1,209 @@ 
     207@@ -0,0 +1,213 @@ 
    318208+/* 
    319209+ * This program is free software; you can redistribute it and/or modify it 
     
    433323+}; 
    434324+ 
     325+phys_addr_t mips_cpc_default_phys_base() { 
     326+       panic("Cannot detect cpc address"); 
     327+} 
     328+ 
    435329+void __init ralink_clk_init(void) 
    436330+{ 
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