Changeset 45633


Ignore:
Timestamp:
2015-05-08T14:23:45+02:00 (3 years ago)
Author:
nbd
Message:

ar71xx: fix ethernet on wnr2000-v4

Most people report broken ethernet with upstream. Last year, user "franz.flasch"
authored a working mach-file. His patch is outdated so I modernized it. Original
patch and user commentary on page 1:
https://forum.openwrt.org/viewtopic.php?pid=260861#p260861

I have figured out what the critical differences are between the two that caused
upstream ethernet to break.

1) Both ath79_init_mac() functions calls must be invocated before any GMAC init
2) must init GMAC0 before GMAC1

That was enough to get upstream to function, but I wanted to enjoy my confidence
having tested franz's patch for a week sucessfully, so I put his whole
function in, which only features more differences in order of function calls.

An expert should consider these changes, which could pose potential bugs/issues:
1) No longer using the flag AR934X_ETH_CFG_SW_PHY_SWAP in the
ath79_setup_ar934x_eth_cfg() call.

2) Possible consequence of no longer explicitly setting ethernet duplex/speed.

Review: With this patch, my ethernet and wireless works.

Signed-off-by: Michael J. Bazzinotti <mbazzinotti@…>

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c

    r45630 r45633  
    123123{ 
    124124        u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); 
    125         u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); 
     125        u8 *ee  = (u8 *) KSEG1ADDR(0x1fff1000); 
     126 
     127        ath79_register_mdio(1, 0x0); 
     128 
     129        ath79_register_usb(); 
    126130 
    127131        ath79_register_m25p80(NULL); 
    128132 
    129         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE | 
    130                                    AR934X_ETH_CFG_SW_PHY_SWAP); 
     133        ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); 
    131134 
    132         ath79_register_mdio(1, 0x0); 
     135        ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0); 
     136        ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0); 
    133137 
    134         /* LAN */ 
    135         ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0); 
    136  
    137         /* GMAC1 is connected to the internal switch */ 
    138         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; 
    139         ath79_register_eth(1); 
    140  
    141         /* WAN */ 
    142         ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0); 
    143  
    144         /* GMAC0 is connected to the PHY0 of the internal switch */ 
     138        /* GMAC0 is connected to the PHY0 of the internal switch, GE0 */ 
    145139        ath79_switch_data.phy4_mii_en = 1; 
    146140        ath79_switch_data.phy_poll_mask = BIT(4); 
     
    148142        ath79_eth0_data.phy_mask = BIT(4); 
    149143        ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; 
    150  
    151         ath79_eth0_data.speed = SPEED_100; 
    152         ath79_eth0_data.duplex = DUPLEX_FULL; 
    153  
    154144        ath79_register_eth(0); 
    155145 
    156         /* WLAN */ 
    157         ath79_register_wmac(ee, art+WNR2000V4_MAC0_OFFSET); 
     146        /* GMAC1 is connected to the internal switch, GE1 */ 
     147        ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; 
     148        ath79_register_eth(1); 
    158149 
    159         /* USB */ 
    160         ath79_register_usb(); 
     150        ath79_register_wmac(ee, art); 
    161151} 
    162152 
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