Changeset 42454


Ignore:
Timestamp:
2014-09-09T10:03:34+02:00 (3 years ago)
Author:
nbd
Message:

ath9k: fix pll clock initialization on newer soc devices (fixes #14916)

Signed-off-by: Felix Fietkau <nbd@…>

Backport of r42453

Location:
branches/barrier_breaker/package/kernel/mac80211/patches
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • branches/barrier_breaker/package/kernel/mac80211/patches/300-pending_work.patch

    r42444 r42454  
     1commit 11f17631d9bf2a9e910dac7d09ba4581f5693831 
     2Author: Felix Fietkau <nbd@openwrt.org> 
     3Date:   Tue Sep 9 09:48:30 2014 +0200 
     4 
     5    ath9k_hw: fix PLL clock initialization for newer SoC 
     6     
     7    On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL 
     8    register changed. This currently breaks at least 5/10 MHz operation. 
     9    AR933x uses the old layout. 
     10     
     11    It might also have been causing other stability issues because of the 
     12    different location of the PLL_BYPASS bit which needs to be set during 
     13    PLL clock initialization. 
     14     
     15    This patch also removes more instances of hardcoded register values in 
     16    favor of properly computed ones with the PLL_BYPASS bit added. 
     17     
     18    Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 
     19    Signed-off-by: Felix Fietkau <nbd@openwrt.org> 
     20 
    121commit 0fecedddd4a0945873db1bd230ec6a168b3cc4fe 
    222Author: Felix Fietkau <nbd@openwrt.org> 
     
    31673187                if (level != aniState->spurImmunityLevel) { 
    31683188                        ath_dbg(common, ANI, 
     3189--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c 
     3190+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c 
     3191@@ -517,6 +517,23 @@ static void ar9003_hw_spur_mitigate(stru 
     3192        ar9003_hw_spur_mitigate_ofdm(ah, chan); 
     3193 } 
     3194  
     3195+static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, 
     3196+                                            struct ath9k_channel *chan) 
     3197+{ 
     3198+       u32 pll; 
     3199+ 
     3200+       pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); 
     3201+ 
     3202+       if (chan && IS_CHAN_HALF_RATE(chan)) 
     3203+               pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); 
     3204+       else if (chan && IS_CHAN_QUARTER_RATE(chan)) 
     3205+               pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); 
     3206+ 
     3207+       pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); 
     3208+ 
     3209+       return pll; 
     3210+} 
     3211+ 
     3212 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 
     3213                                         struct ath9k_channel *chan) 
     3214 { 
     3215@@ -1779,7 +1796,12 @@ void ar9003_hw_attach_phy_ops(struct ath 
     3216  
     3217        priv_ops->rf_set_freq = ar9003_hw_set_channel; 
     3218        priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 
     3219-       priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 
     3220+ 
     3221+       if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 
     3222+               priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; 
     3223+       else 
     3224+               priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 
     3225+ 
     3226        priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 
     3227        priv_ops->init_bb = ar9003_hw_init_bb; 
     3228        priv_ops->process_ini = ar9003_hw_process_ini; 
     3229--- a/drivers/net/wireless/ath/ath9k/hw.c 
     3230+++ b/drivers/net/wireless/ath/ath9k/hw.c 
     3231@@ -702,6 +702,8 @@ static void ath9k_hw_init_pll(struct ath 
     3232 { 
     3233        u32 pll; 
     3234  
     3235+       pll = ath9k_hw_compute_pll_control(ah, chan); 
     3236+ 
     3237        if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 
     3238                /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 
     3239                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 
     3240@@ -752,7 +754,8 @@ static void ath9k_hw_init_pll(struct ath 
     3241                REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 
     3242                              AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 
     3243  
     3244-               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 
     3245+               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 
     3246+                         pll | AR_RTC_9300_PLL_BYPASS); 
     3247                udelay(1000); 
     3248  
     3249                /* program refdiv, nint, frac to RTC register */ 
     3250@@ -768,7 +771,8 @@ static void ath9k_hw_init_pll(struct ath 
     3251        } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 
     3252                u32 regval, pll2_divint, pll2_divfrac, refdiv; 
     3253  
     3254-               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 
     3255+               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 
     3256+                         pll | AR_RTC_9300_SOC_PLL_BYPASS); 
     3257                udelay(1000); 
     3258  
     3259                REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 
     3260@@ -840,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath 
     3261                udelay(1000); 
     3262        } 
     3263  
     3264-       pll = ath9k_hw_compute_pll_control(ah, chan); 
     3265        if (AR_SREV_9565(ah)) 
     3266                pll |= 0x40000; 
     3267        REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 
     3268--- a/drivers/net/wireless/ath/ath9k/reg.h 
     3269+++ b/drivers/net/wireless/ath/ath9k/reg.h 
     3270@@ -1236,12 +1236,23 @@ enum { 
     3271 #define AR_CH0_DPLL3_PHASE_SHIFT_S   23 
     3272 #define AR_PHY_CCA_NOM_VAL_2GHZ      -118 
     3273  
     3274+#define AR_RTC_9300_SOC_PLL_DIV_INT          0x0000003f 
     3275+#define AR_RTC_9300_SOC_PLL_DIV_INT_S        0 
     3276+#define AR_RTC_9300_SOC_PLL_DIV_FRAC         0x000fffc0 
     3277+#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S       6 
     3278+#define AR_RTC_9300_SOC_PLL_REFDIV           0x01f00000 
     3279+#define AR_RTC_9300_SOC_PLL_REFDIV_S         20 
     3280+#define AR_RTC_9300_SOC_PLL_CLKSEL           0x06000000 
     3281+#define AR_RTC_9300_SOC_PLL_CLKSEL_S         25 
     3282+#define AR_RTC_9300_SOC_PLL_BYPASS           0x08000000 
     3283+ 
     3284 #define AR_RTC_9300_PLL_DIV          0x000003ff 
     3285 #define AR_RTC_9300_PLL_DIV_S        0 
     3286 #define AR_RTC_9300_PLL_REFDIV       0x00003C00 
     3287 #define AR_RTC_9300_PLL_REFDIV_S     10 
     3288 #define AR_RTC_9300_PLL_CLKSEL       0x0000C000 
     3289 #define AR_RTC_9300_PLL_CLKSEL_S     14 
     3290+#define AR_RTC_9300_PLL_BYPASS       0x00010000 
     3291  
     3292 #define AR_RTC_9160_PLL_DIV    0x000003ff 
     3293 #define AR_RTC_9160_PLL_DIV_S   0 
  • branches/barrier_breaker/package/kernel/mac80211/patches/523-ath9k_use_configured_antenna_gain.patch

    r40834 r42454  
    1111--- a/drivers/net/wireless/ath/ath9k/hw.c 
    1212+++ b/drivers/net/wireless/ath/ath9k/hw.c 
    13 @@ -2721,7 +2721,7 @@ void ath9k_hw_apply_txpower(struct ath_h 
     13@@ -2724,7 +2724,7 @@ void ath9k_hw_apply_txpower(struct ath_h 
    1414        channel = chan->chan; 
    1515        chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 
  • branches/barrier_breaker/package/kernel/mac80211/patches/542-ath9k_debugfs_diag.patch

    r40834 r42454  
    9595--- a/drivers/net/wireless/ath/ath9k/hw.c 
    9696+++ b/drivers/net/wireless/ath/ath9k/hw.c 
    97 @@ -1735,6 +1735,20 @@ fail: 
     97@@ -1738,6 +1738,20 @@ fail: 
    9898        return -EINVAL; 
    9999 } 
     
    116116                   struct ath9k_hw_cal_data *caldata, bool fastcc) 
    117117 { 
    118 @@ -1940,6 +1954,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
     118@@ -1943,6 +1957,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
    119119                ar9003_hw_disable_phy_restart(ah); 
    120120  
  • branches/barrier_breaker/package/kernel/mac80211/patches/543-ath9k-allow-to-disable-bands-via-platform-data.patch

    r40800 r42454  
    1212--- a/drivers/net/wireless/ath/ath9k/hw.c 
    1313+++ b/drivers/net/wireless/ath/ath9k/hw.c 
    14 @@ -2328,17 +2328,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw 
     14@@ -2331,17 +2331,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw 
    1515        } 
    1616  
  • branches/barrier_breaker/package/kernel/mac80211/patches/550-ath9k_entropy_from_adc.patch

    r42444 r42454  
    1919--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c 
    2020+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c 
    21 @@ -1764,6 +1764,26 @@ static void ar9003_hw_tx99_set_txpower(s 
     21@@ -1781,6 +1781,26 @@ static void ar9003_hw_tx99_set_txpower(s 
    2222                  ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14],  0)); 
    2323 } 
     
    4646 { 
    4747        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 
    48 @@ -1794,6 +1814,7 @@ void ar9003_hw_attach_phy_ops(struct ath 
     48@@ -1816,6 +1836,7 @@ void ar9003_hw_attach_phy_ops(struct ath 
    4949        priv_ops->set_radar_params = ar9003_hw_set_radar_params; 
    5050        priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 
  • branches/barrier_breaker/package/kernel/mac80211/patches/551-ath9k-ar933x-usb-hang-workaround.patch

    r40800 r42454  
    2121 /* Chip Revisions */ 
    2222 /******************/ 
    23 @@ -1337,6 +1350,9 @@ static bool ath9k_hw_set_reset(struct at 
     23@@ -1340,6 +1353,9 @@ static bool ath9k_hw_set_reset(struct at 
    2424        if (AR_SREV_9100(ah)) 
    2525                udelay(50); 
     
    3131 } 
    3232  
    33 @@ -1436,6 +1452,9 @@ static bool ath9k_hw_chip_reset(struct a 
     33@@ -1439,6 +1455,9 @@ static bool ath9k_hw_chip_reset(struct a 
    3434                ar9003_hw_internal_regulator_apply(ah); 
    3535        ath9k_hw_init_pll(ah, chan); 
     
    4141 } 
    4242  
    43 @@ -1730,8 +1749,14 @@ static int ath9k_hw_do_fastcc(struct ath 
     43@@ -1733,8 +1752,14 @@ static int ath9k_hw_do_fastcc(struct ath 
    4444        if (AR_SREV_9271(ah)) 
    4545                ar9002_hw_load_ani_reg(ah, chan); 
     
    5656 } 
    5757  
    58 @@ -1959,6 +1984,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
     58@@ -1962,6 +1987,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
    5959        if (AR_SREV_9565(ah) && common->bt_ant_diversity) 
    6060                REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 
  • branches/barrier_breaker/package/kernel/mac80211/patches/562-ath9k_ani_ws_detect.patch

    r41028 r42454  
    8080  * ar9003_hw_set_channel - set channel on single-chip device 
    8181  * @ah: atheros hardware structure 
    82 @@ -954,11 +940,6 @@ static bool ar9003_hw_ani_control(struct 
     82@@ -971,11 +957,6 @@ static bool ar9003_hw_ani_control(struct 
    8383        struct ath_common *common = ath9k_hw_common(ah); 
    8484        struct ath9k_channel *chan = ah->curchan; 
     
    9292  
    9393        switch (cmd & ah->ani_function) { 
    94 @@ -972,61 +953,6 @@ static bool ar9003_hw_ani_control(struct 
     94@@ -989,61 +970,6 @@ static bool ar9003_hw_ani_control(struct 
    9595                 */ 
    9696                u32 on = param ? 1 : 0; 
  • branches/barrier_breaker/package/kernel/mac80211/patches/565-ath9k_restart_after_nfcal_failure.patch

    r41113 r42454  
    153153--- a/drivers/net/wireless/ath/ath9k/link.c 
    154154+++ b/drivers/net/wireless/ath/ath9k/link.c 
    155 @@ -376,9 +376,14 @@ void ath_ani_calibrate(unsigned long dat 
     155@@ -371,9 +371,14 @@ void ath_ani_calibrate(unsigned long dat 
    156156  
    157157        /* Perform calibration if necessary */ 
  • branches/barrier_breaker/package/kernel/mac80211/patches/567-ath9k_fix_init_nfcal.patch

    r41156 r42454  
    1111--- a/drivers/net/wireless/ath/ath9k/hw.c 
    1212+++ b/drivers/net/wireless/ath/ath9k/hw.c 
    13 @@ -1969,8 +1969,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
     13@@ -1972,8 +1972,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st 
    1414        if (ath9k_hw_mci_is_enabled(ah)) 
    1515                ar9003_mci_check_bt(ah); 
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