Changeset 36014
- Timestamp:
- 2013-03-14T19:42:29+01:00 (5 years ago)
- Location:
- trunk/target/linux/lantiq
- Files:
-
- 20 added
- 1 edited
- 23 copied
Legend:
- Unmodified
- Added
- Removed
-
trunk/target/linux/lantiq/Makefile
r35860 r36014 12 12 SUBTARGETS=xway ase falcon 13 13 14 LINUX_VERSION:=3. 7.1014 LINUX_VERSION:=3.8.2 15 15 16 16 CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -fno-caller-saves -mno-branch-likely -
trunk/target/linux/lantiq/patches-3.8/0004-Document-devicetree-add-OF-documents-for-lantiq-seri.patch
r36013 r36014 1 From ed881db69430dd62765d02e2f4f1321ddc2f5fb5Mon Sep 17 00:00:00 20011 From 8cd55f4107a3acda4793ed282a114af2f4cb4983 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Fri, 20 Jul 2012 18:58:34 +0200 4 Subject: [PATCH 110/123] Document: devicetree: add OF documents for lantiq4 Subject: [PATCH 04/40] Document: devicetree: add OF documents for lantiq 5 5 serial port 6 6 … … 13 13 create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt 14 14 15 diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt 16 new file mode 100644 17 index 0000000..5b78591 15 18 --- /dev/null 16 19 +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt … … 32 35 + interrupts = <112 113 114>; 33 36 +}; 37 -- 38 1.7.10.4 39 -
trunk/target/linux/lantiq/patches-3.8/0005-PINCTRL-lantiq-pinconf-uses-port-instead-of-pin.patch
r36013 r36014 1 From 84ce6d4b2802fd428a76e5f2692fd4c102ed35eaMon Sep 17 00:00:00 20011 From 5e19578b807e7ef6e7baf05fb1f69433d5e74667 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Fri, 30 Nov 2012 21:11:22 +0100 4 Subject: [PATCH 107/123] PINCTRL: lantiq: pinconf uses port instead of pin4 Subject: [PATCH 05/40] PINCTRL: lantiq: pinconf uses port instead of pin 5 5 6 6 The XWAY pinctrl driver invalidly uses the port and not the pin number to work … … 13 13 1 file changed, 14 insertions(+), 14 deletions(-) 14 14 15 diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c 16 index 5f0eb04..69dec9b 100644 15 17 --- a/drivers/pinctrl/pinctrl-xway.c 16 18 +++ b/drivers/pinctrl/pinctrl-xway.c 17 @@ -441,17 +441,17 @@ static int xway_pinconf_get(struct pinct 19 @@ -441,17 +441,17 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev, 18 20 if (port == PORT3) 19 21 reg = GPIO3_OD; … … 37 39 break; 38 40 } 39 @@ -459,8 +459,8 @@ static int xway_pinconf_get(struct pinct 41 @@ -459,8 +459,8 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev, 40 42 if (port == PORT3) 41 43 reg = GPIO3_PUDSEL; … … 48 50 else 49 51 *config = LTQ_PINCONF_PACK(param, 1); 50 @@ -488,29 +488,29 @@ static int xway_pinconf_set(struct pinct 52 @@ -488,29 +488,29 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev, 51 53 if (port == PORT3) 52 54 reg = GPIO3_OD; … … 86 88 dev_err(pctldev->dev, "Invalid pull value %d\n", arg); 87 89 break; 90 -- 91 1.7.10.4 92 -
trunk/target/linux/lantiq/patches-3.8/0017-MIPS-lantiq-adds-static-clock-for-PP32.patch
r36013 r36014 1 From 8cbac4b30bed1552503b95bc0ac6276e3cdda9d8Mon Sep 17 00:00:00 20011 From 46a704b1b093f4053eceaf8e5f0ab54949afa532 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Fri, 30 Nov 2012 21:08:49 +01004 Subject: [PATCH 1 03/123] MIPS: lantiq: adds static clock for PP323 Date: Sat, 19 Jan 2013 08:54:24 +0000 4 Subject: [PATCH 17/40] MIPS: lantiq: adds static clock for PP32 5 5 6 6 The Lantiq DSL SoCs have an internal networking processor. Add code to read … … 8 8 9 9 Signed-off-by: John Crispin <blogic@openwrt.org> 10 Patchwork: http://patchwork.linux-mips.org/patch/4815/ 10 11 --- 11 12 arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + … … 17 18 6 files changed, 69 insertions(+), 10 deletions(-) 18 19 20 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h 21 index 5e8a6e9..76be7a0 100644 19 22 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h 20 23 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h 21 @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *c 24 @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *clk); 22 25 extern struct clk *clk_get_cpu(void); 23 26 extern struct clk *clk_get_fpi(void); … … 27 30 /* find out what bootsource we have */ 28 31 extern unsigned char ltq_boot_select(void); 32 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c 33 index ce2f129..d903560 100644 29 34 --- a/arch/mips/lantiq/clk.c 30 35 +++ b/arch/mips/lantiq/clk.c … … 60 65 { 61 66 return clk && !IS_ERR(clk); 67 diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h 68 index fa67060..77e4bdb 100644 62 69 --- a/arch/mips/lantiq/clk.h 63 70 +++ b/arch/mips/lantiq/clk.h … … 78 85 #define CLOCK_600M 600000000 79 86 80 @@ -64,1 6 +67,18@@ struct clk {87 @@ -64,15 +67,17 @@ struct clk { 81 88 }; 82 89 … … 96 103 +extern unsigned long ltq_vr9_pp32_hz(void); 97 104 98 extern unsigned long ltq_svip_cpu_hz(void); 99 extern unsigned long ltq_svip_fpi_hz(void); 105 #endif 106 diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c 107 index 2d4ced3..ff4894a 100644 100 108 --- a/arch/mips/lantiq/falcon/sysctrl.c 101 109 +++ b/arch/mips/lantiq/falcon/sysctrl.c … … 112 120 /* add our clock domains */ 113 121 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); 122 diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c 123 index 9aa17f7..1ab576d 100644 114 124 --- a/arch/mips/lantiq/xway/clk.c 115 125 +++ b/arch/mips/lantiq/xway/clk.c … … 144 154 { 145 155 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) 146 @@ -147,5 +170,25 @@ unsigned long ltq_vr9_fpi_hz(void) 147 break; 148 } 149 150 + return clk; 151 +} 156 @@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void) 157 158 return clk; 159 } 152 160 + 153 161 +unsigned long ltq_vr9_pp32_hz(void) … … 168 176 + } 169 177 + 170 return clk; 171 } 178 + return clk; 179 +} 180 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c 181 index 1aaa726..3390fcd 100644 172 182 --- a/arch/mips/lantiq/xway/sysctrl.c 173 183 +++ b/arch/mips/lantiq/xway/sysctrl.c … … 192 202 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); 193 203 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); 194 @@ -37 7,10 +379,10 @@ void __init ltq_soc_init(void)195 clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);204 @@ -376,10 +378,10 @@ void __init ltq_soc_init(void) 205 PMU_PPE_QSB | PMU_PPE_TOP); 196 206 } else if (of_machine_is_compatible("lantiq,ar9")) { 197 207 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), … … 205 215 } 206 216 } 217 -- 218 1.7.10.4 219 -
trunk/target/linux/lantiq/patches-3.8/0019-MIPS-lantiq-rework-external-irq-code.patch
r36013 r36014 1 From edd237c93d564e698e169a89d1b1b35248c5ef4aMon Sep 17 00:00:00 20011 From d8f6bf3fb606ee8fdd5b7aff4aedb54e30792b84 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Mon, 3 Dec 2012 21:44:30 +01004 Subject: [PATCH 1 05/123] MIPS: lantiq: rework external irq code3 Date: Sat, 19 Jan 2013 08:54:27 +0000 4 Subject: [PATCH 19/40] MIPS: lantiq: rework external irq code 5 5 6 6 This code makes the irqs used by the EIU loadable from the DT. Additionally we … … 9 9 10 10 Signed-off-by: John Crispin <blogic@openwrt.org> 11 Patchwork: http://patchwork.linux-mips.org/patch/4818/ 11 12 --- 12 13 arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + 13 arch/mips/lantiq/irq.c | 104 +++++++++++++++++++--------- 14 2 files changed, 73 insertions(+), 32 deletions(-) 15 14 arch/mips/lantiq/irq.c | 105 +++++++++++++++++++--------- 15 2 files changed, 74 insertions(+), 32 deletions(-) 16 17 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h 18 index 76be7a0..f196cce 100644 16 19 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h 17 20 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h … … 24 27 /* clock handling */ 25 28 extern int clk_activate(struct clk *clk); 29 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c 30 index a7935bf..5119487 100644 26 31 --- a/arch/mips/lantiq/irq.c 27 32 +++ b/arch/mips/lantiq/irq.c … … 75 80 { 76 81 u32 ier = LTQ_ICU_IM0_IER; 77 @@ -128,19 +120,6 4@@ void ltq_enable_irq(struct irq_data *d)82 @@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d) 78 83 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); 79 84 } … … 110 115 + break; 111 116 + default: 112 + pr_err("invalid type %d for irq %ld\n", type, d->hwirq); 117 + pr_err("invalid type %d for irq %ld\n", 118 + type, d->hwirq); 113 119 + return -EINVAL; 114 120 + } … … 146 152 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), 147 153 LTQ_EIU_EXIN_INEN); 148 @@ -157,7 +19 4,7 @@ static void ltq_shutdown_eiu_irq(struct154 @@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d) 149 155 150 156 ltq_disable_irq(d); … … 155 161 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), 156 162 LTQ_EIU_EXIN_INEN); 157 @@ -186,6 +22 3,7 @@ static struct irq_chip ltq_eiu_type = {163 @@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = { 158 164 .irq_ack = ltq_ack_irq, 159 165 .irq_mask = ltq_disable_irq, … … 163 169 164 170 static void ltq_hw_irqdispatch(int module) 165 @@ -301,7 +3 39,7 @@ static int icu_map(struct irq_domain *d,171 @@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 166 172 return 0; 167 173 … … 172 178 173 179 irq_set_chip_and_handler(hw, chip, handle_level_irq); 174 @@ -323,7 +36 1,7 @@ int __init icu_of_init(struct device_nod180 @@ -323,7 +362,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) 175 181 { 176 182 struct device_node *eiu_node; … … 181 187 for (i = 0; i < MAX_IM; i++) { 182 188 if (of_address_to_resource(node, i, &res)) 183 @@ -340,17 +37 8,19 @@ int __init icu_of_init(struct device_nod189 @@ -340,17 +379,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) 184 190 } 185 191 … … 206 212 res.name) < 0) 207 213 pr_err("Failed to request eiu memory"); 214 -- 215 1.7.10.4 216 -
trunk/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch
r36013 r36014 1 From 07f7321c0f79c0b800d28898a480d044f839e813Mon Sep 17 00:00:00 20011 From 5be3837d01ea56e1455781f1b51764bd896973f2 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Thu, 6 Dec 2012 11:59:23 +0100 4 Subject: [PATCH 104/123] MIPS: lantiq: adds 4dword burst length for dma4 Subject: [PATCH 20/40] MIPS: lantiq: adds 4dword burst length for dma 5 5 6 6 --- … … 8 8 1 file changed, 3 insertions(+), 1 deletion(-) 9 9 10 diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c 11 index e44a186..c7684c9 100644 10 12 --- a/arch/mips/lantiq/xway/dma.c 11 13 +++ b/arch/mips/lantiq/xway/dma.c … … 17 19 #define DMA_2W_BURST BIT(1) /* 2 word burst length */ 18 20 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ 19 #define DMA_ETOP_ENDIAN ESS (0xf << 8) /* endianess swap etop channels */21 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ 20 22 @@ -195,7 +196,8 @@ ltq_dma_init_port(int p) 21 * Tell the DMA engine to swap the endian ess of data frames and23 * Tell the DMA engine to swap the endianness of data frames and 22 24 * drop packets if the channel arbitration fails. 23 25 */ 24 - ltq_dma_w32_mask(0, DMA_ETOP_ENDIAN ESS | DMA_PDEN,26 - ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, 25 27 + ltq_dma_w32_mask(0, (DMA_4W_BURST << 4) | (DMA_4W_BURST << 2) | 26 + DMA_ETOP_ENDIAN ESS | DMA_PDEN,28 + DMA_ETOP_ENDIANNESS | DMA_PDEN, 27 29 LTQ_DMA_PCTRL); 28 30 break; 29 31 32 -- 33 1.7.10.4 34 -
trunk/target/linux/lantiq/patches-3.8/0021-GPIO-MIPS-add-gpio-driver-for-falcon-SoC.patch
r36013 r36014 1 From d4911be1cc44c8d3ca72b03d5da13f792d4a02d2Mon Sep 17 00:00:00 20011 From ff3d0dd789882ad552a5224d34e5db426e1c45fe Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Sat, 23 Jun 2012 15:32:33 +0200 4 Subject: [PATCH 109/123] GPIO: MIPS: add gpio driver for falcon SoC4 Subject: [PATCH 21/40] GPIO: MIPS: add gpio driver for falcon SoC 5 5 6 6 Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of … … 17 17 create mode 100644 drivers/gpio/gpio-falcon.c 18 18 19 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig 20 index 682de75..e8d84fa 100644 19 21 --- a/drivers/gpio/Kconfig 20 22 +++ b/drivers/gpio/Kconfig 21 @@ -1 14,6 +114,11 @@ config GPIO_EP93XX23 @@ -133,6 +133,11 @@ config GPIO_EP93XX 22 24 depends on ARCH_EP93XX 23 25 select GPIO_GENERIC … … 31 33 bool "Lantiq Memory mapped GPIOs" 32 34 depends on LANTIQ && SOC_XWAY 35 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile 36 index c5aebd0..9bdbb91 100644 33 37 --- a/drivers/gpio/Makefile 34 38 +++ b/drivers/gpio/Makefile 35 @@ -2 1,6 +21,7 @@ obj-$(CONFIG_GPIO_DA9052) += gpio-da905239 @@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o 36 40 obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o 37 41 obj-$(CONFIG_GPIO_EM) += gpio-em.o … … 41 45 obj-$(CONFIG_GPIO_ICH) += gpio-ich.o 42 46 obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o 47 diff --git a/drivers/gpio/gpio-falcon.c b/drivers/gpio/gpio-falcon.c 48 new file mode 100644 49 index 0000000..ae8b55d 43 50 --- /dev/null 44 51 +++ b/drivers/gpio/gpio-falcon.c … … 393 400 + 394 401 +subsys_initcall(falcon_gpio_init); 402 -- 403 1.7.10.4 404 -
trunk/target/linux/lantiq/patches-3.8/0022-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
r36013 r36014 1 From f2ac37c0a5297ca4663da9e4328c77736504b484Mon Sep 17 00:00:00 20011 From 09628160c97e9bd7dfbb39fd467cf17f1e43e85c Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Sun, 20 May 2012 00:42:39 +0200 4 Subject: [PATCH 113/123] I2C: MIPS: lantiq: add FALC-ON i2c bus master4 Subject: [PATCH 22/40] I2C: MIPS: lantiq: add FALC-ON i2c bus master 5 5 6 6 This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. … … 17 17 create mode 100644 drivers/i2c/busses/i2c-lantiq.h 18 18 19 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig 20 index bdca511..5e2994f 100644 19 21 --- a/drivers/i2c/busses/Kconfig 20 22 +++ b/drivers/i2c/busses/Kconfig 21 @@ -4 60,6 +460,16 @@ config I2C_IOP3XX23 @@ -470,6 +470,16 @@ config I2C_IOP3XX 22 24 This driver can also be built as a module. If so, the module 23 25 will be called i2c-iop3xx. … … 36 38 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" 37 39 depends on PPC 40 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile 41 index 6181f3f..40ea7d8 100644 38 42 --- a/drivers/i2c/busses/Makefile 39 43 +++ b/drivers/i2c/busses/Makefile 40 @@ -4 5,6 +45,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic44 @@ -46,6 +46,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 41 45 obj-$(CONFIG_I2C_IMX) += i2c-imx.o 42 46 obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o … … 46 50 obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 47 51 obj-$(CONFIG_I2C_MXS) += i2c-mxs.o 52 diff --git a/drivers/i2c/busses/i2c-lantiq.c b/drivers/i2c/busses/i2c-lantiq.c 53 new file mode 100644 54 index 0000000..9a5f58b 48 55 --- /dev/null 49 56 +++ b/drivers/i2c/busses/i2c-lantiq.c … … 796 803 +MODULE_LICENSE("GPL"); 797 804 +MODULE_VERSION(DRV_VERSION); 805 diff --git a/drivers/i2c/busses/i2c-lantiq.h b/drivers/i2c/busses/i2c-lantiq.h 806 new file mode 100644 807 index 0000000..7a86b89 798 808 --- /dev/null 799 809 +++ b/drivers/i2c/busses/i2c-lantiq.h … … 1033 1043 + 1034 1044 +#endif /* I2C_LANTIQ_H */ 1045 -- 1046 1.7.10.4 1047 -
trunk/target/linux/lantiq/patches-3.8/0023-USB-fix-roothub-for-IFXHCD.patch
r36013 r36014 1 From 1b6941ae603f2885e6cf729119ef753deb7eb835 Mon Sep 17 00:00:00 20011 From e6c3c0d86a581e0738e18e5a3369ded8527a3315 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Thu, 6 Dec 2012 19:59:53 +0100 4 Subject: [PATCH 123/123] USB: fix roothub for IFXHCD4 Subject: [PATCH 23/40] USB: fix roothub for IFXHCD 5 5 6 6 --- 7 drivers/usb/core/hub.c | 2 +- 8 1 file changed, 1 insertion(+), 1 deletion(-) 7 arch/mips/lantiq/Kconfig | 1 + 8 drivers/usb/core/hub.c | 2 +- 9 2 files changed, 2 insertions(+), 1 deletion(-) 9 10 10 --- a/drivers/usb/core/hub.c 11 +++ b/drivers/usb/core/hub.c 12 @@ -3940,7 +3940,7 @@ hub_port_init (struct usb_hub *hub, stru 13 udev->ttport = hdev->ttport; 14 } else if (udev->speed != USB_SPEED_HIGH 15 && hdev->speed == USB_SPEED_HIGH) { 16 - if (!hub->tt.hub) { 17 + if (hdev->parent && !hub->tt.hub) { 18 dev_err(&udev->dev, "parent hub has no TT\n"); 19 retval = -EINVAL; 20 goto fail; 11 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig 12 index c002191..675310a 100644 21 13 --- a/arch/mips/lantiq/Kconfig 22 14 +++ b/arch/mips/lantiq/Kconfig … … 29 21 30 22 choice 23 diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c 24 index cbf7168..5cddead 100644 25 --- a/drivers/usb/core/hub.c 26 +++ b/drivers/usb/core/hub.c 27 @@ -4006,7 +4006,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, 28 udev->ttport = hdev->ttport; 29 } else if (udev->speed != USB_SPEED_HIGH 30 && hdev->speed == USB_SPEED_HIGH) { 31 - if (!hub->tt.hub) { 32 + if (hdev->parent && !hub->tt.hub) { 33 dev_err(&udev->dev, "parent hub has no TT\n"); 34 retval = -EINVAL; 35 goto fail; 36 -- 37 1.7.10.4 38 -
trunk/target/linux/lantiq/patches-3.8/0024-SPI-MIPS-lantiq-adds-spi-xway.patch
r36013 r36014 1 From db447f1a18106aa4d32438ab72ff57024b34cee4Mon Sep 17 00:00:00 20011 From 60092075ded3e51036fd018ba6d9cc49e7079dcd Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Thu, 16 Aug 2012 09:57:01 +02004 Subject: [PATCH 114/123] SPI: MIPS: lantiq: adds spi-xway3 Date: Wed, 13 Mar 2013 09:29:37 +0100 4 Subject: [PATCH 24/40] SPI: MIPS: lantiq: adds spi-xway 5 5 6 6 This patch adds support for the SPI core found on several Lantiq SoCs. … … 17 17 create mode 100644 drivers/spi/spi-xway.c 18 18 19 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig 20 index 2e188e1..3522f29 100644 19 21 --- a/drivers/spi/Kconfig 20 22 +++ b/drivers/spi/Kconfig 21 @@ -44 3,6 +443,14 @@ config SPI_NUC90023 @@ -449,6 +449,14 @@ config SPI_NUC900 22 24 help 23 25 SPI driver for Nuvoton NUC900 series ARM SoCs … … 34 36 # Add new SPI master controllers in alphabetical order above this line 35 37 # 38 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile 39 index 64e970b..63c24da 100644 36 40 --- a/drivers/spi/Makefile 37 41 +++ b/drivers/spi/Makefile 38 @@ -6 7,4 +67,5 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-t42 @@ -68,3 +68,4 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o 39 43 obj-$(CONFIG_SPI_TXX9) += spi-txx9.o 40 44 obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o 41 45 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o 42 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o 43 46 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o 47 diff --git a/drivers/spi/spi-xway.c b/drivers/spi/spi-xway.c 48 new file mode 100644 49 index 0000000..61532e3 44 50 --- /dev/null 45 51 +++ b/drivers/spi/spi-xway.c … … 821 827 +}; 822 828 + 823 +static int __devinitltq_spi_probe(struct platform_device *pdev)829 +static int ltq_spi_probe(struct platform_device *pdev) 824 830 +{ 825 831 + struct resource irqres[3]; … … 972 978 +} 973 979 + 974 +static int __devexitltq_spi_remove(struct platform_device *pdev)980 +static int ltq_spi_remove(struct platform_device *pdev) 975 981 +{ 976 982 + struct ltq_spi *hw = platform_get_drvdata(pdev); … … 1008 1014 +static struct platform_driver ltq_spi_driver = { 1009 1015 + .probe = ltq_spi_probe, 1010 + .remove = __devexit_p(ltq_spi_remove),1016 + .remove = ltq_spi_remove, 1011 1017 + .driver = { 1012 1018 + .name = "spi-xway", … … 1022 1028 +MODULE_LICENSE("GPL"); 1023 1029 +MODULE_ALIAS("platform:spi-xway"); 1030 -- 1031 1.7.10.4 1032 -
trunk/target/linux/lantiq/patches-3.8/0025-NET-MIPS-lantiq-adds-xrx200-net.patch
r36013 r36014 1 From a0a6f7f03c914327064364767b7ba688cdbcf611 Mon Sep 17 00:00:00 20011 From fbfdf78ba827a8f854ae3ed7b11ea6df4054ffb1 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Mon, 22 Oct 2012 12:22:23 +0200 4 Subject: [PATCH 117/123] NET: MIPS: lantiq: adds xrx200-net4 Subject: [PATCH 25/40] NET: MIPS: lantiq: adds xrx200-net 5 5 6 6 --- … … 8 8 drivers/net/ethernet/Makefile | 1 + 9 9 drivers/net/ethernet/lantiq_pce.h | 163 +++++ 10 drivers/net/ethernet/lantiq_xrx200.c | 1 191++++++++++++++++++++++++++++++++++11 4 files changed, 13 62insertions(+), 1 deletion(-)10 drivers/net/ethernet/lantiq_xrx200.c | 1203 ++++++++++++++++++++++++++++++++++ 11 4 files changed, 1374 insertions(+), 1 deletion(-) 12 12 create mode 100644 drivers/net/ethernet/lantiq_pce.h 13 13 create mode 100644 drivers/net/ethernet/lantiq_xrx200.c 14 14 15 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig 16 index e4ff389..35cb7b0 100644 15 17 --- a/drivers/net/ethernet/Kconfig 16 18 +++ b/drivers/net/ethernet/Kconfig … … 30 32 source "drivers/net/ethernet/marvell/Kconfig" 31 33 source "drivers/net/ethernet/mellanox/Kconfig" 34 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile 35 index d447307..4f95100 100644 32 36 --- a/drivers/net/ethernet/Makefile 33 37 +++ b/drivers/net/ethernet/Makefile … … 40 44 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ 41 45 obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ 46 diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h 47 new file mode 100644 48 index 0000000..0c38efe 42 49 --- /dev/null 43 50 +++ b/drivers/net/ethernet/lantiq_pce.h … … 206 213 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), 207 214 +}; 215 diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c 216 new file mode 100644 217 index 0000000..f815165 208 218 --- /dev/null 209 219 +++ b/drivers/net/ethernet/lantiq_xrx200.c … … 1285 1295 +static struct xrx200_hw xrx200_hw; 1286 1296 + 1287 +static int __devinitxrx200_probe(struct platform_device *pdev)1297 +static int xrx200_probe(struct platform_device *pdev) 1288 1298 +{ 1289 1299 + struct resource *res[4]; … … 1366 1376 +} 1367 1377 + 1368 +static int __devexitxrx200_remove(struct platform_device *pdev)1378 +static int xrx200_remove(struct platform_device *pdev) 1369 1379 +{ 1370 1380 + struct net_device *dev = platform_get_drvdata(pdev); … … 1399 1409 +static struct platform_driver xrx200_driver = { 1400 1410 + .probe = xrx200_probe, 1401 + .remove = __devexit_p(xrx200_remove),1411 + .remove = xrx200_remove, 1402 1412 + .driver = { 1403 1413 + .name = "lantiq,xrx200-net", … … 1412 1422 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); 1413 1423 +MODULE_LICENSE("GPL"); 1424 -- 1425 1.7.10.4 1426 -
trunk/target/linux/lantiq/patches-3.8/0026-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
r36013 r36014 1 From c7b0e371e1c5e2f6258decfeb948e0dda7109afcMon Sep 17 00:00:00 20011 From 32010516999c75d8e8ea95779137438f4f6d06ae Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Wed, 24 Oct 2012 19:50:30 +02004 Subject: [PATCH 116/123] NET: MIPS: lantiq: update etop driver for devicetree3 Date: Wed, 13 Mar 2013 09:32:16 +0100 4 Subject: [PATCH 26/40] NET: MIPS: lantiq: update etop driver for devicetree 5 5 6 6 --- 7 drivers/net/ethernet/lantiq_etop.c | 4 70+++++++++++++++++++++++++-----------8 1 file changed, 3 33 insertions(+), 137deletions(-)7 drivers/net/ethernet/lantiq_etop.c | 496 +++++++++++++++++++++++++----------- 8 1 file changed, 351 insertions(+), 145 deletions(-) 9 9 10 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c 11 index c124e67..91a37f1 100644 10 12 --- a/drivers/net/ethernet/lantiq_etop.c 11 13 +++ b/drivers/net/ethernet/lantiq_etop.c … … 30 32 #include <asm/checksum.h> 31 33 32 @@ -71,25 +75, 56@@34 @@ -71,25 +75,61 @@ 33 35 #define ETOP_MII_REVERSE 0xe 34 36 #define ETOP_PLEN_UNDER 0x40 35 37 #define ETOP_CGEN 0x800 36 +#define ETOP_CFG_MII0 0x01 37 38 - 38 39 -/* use 2 static channels for TX/RX */ 39 40 -#define LTQ_ETOP_TX_CHANNEL 1 … … 41 42 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 42 43 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 44 - 45 +#define ETOP_CFG_MII0 0x01 46 + 43 47 +#define LTQ_GBIT_MDIO_CTL 0xCC 44 48 +#define LTQ_GBIT_MDIO_DATA 0xd0 … … 47 51 +#define LTQ_GBIT_P0_CTL 0x4 48 52 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8 53 +#define LTQ_GBIT_RGMII_CTL 0x78 49 54 + 50 55 +#define PMAC_HD_CTL_AS (1 << 19) … … 55 60 +/* Disable MDIO auto polling (0=disable, 1=enable) */ 56 61 +#define PX_CTL_DMDIO 0x00400000 62 + 63 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ 64 +#define MDC_CLOCK_MASK 0xff000000 65 +#define MDC_CLOCK_OFFSET 24 57 66 + 58 67 +/* register information for the gbit's MDIO bus */ … … 66 75 +#define MDIO_XR9_ADDR_OFFSET 5 67 76 +#define MDIO_XR9_WR_OFFSET 16 68 77 + 69 78 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ 70 79 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) … … 94 103 struct napi_struct napi; 95 104 struct ltq_dma_channel dma; 96 @@ -99,22 +13 4,35 @@ struct ltq_etop_chan {105 @@ -99,22 +139,35 @@ struct ltq_etop_chan { 97 106 struct ltq_etop_priv { 98 107 struct net_device *netdev; … … 134 143 return -ENOMEM; 135 144 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, 136 @@ -149,8 + 197,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan145 @@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch) 137 146 spin_unlock_irqrestore(&priv->lock, flags); 138 147 … … 146 155 147 156 static int 148 @@ -158,8 +2 09,10 @@ ltq_etop_poll_rx(struct napi_struct *nap157 @@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) 149 158 { 150 159 struct ltq_etop_chan *ch = container_of(napi, … … 157 166 while ((rx < budget) && !complete) { 158 167 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 159 @@ -173,7 +2 26,9 @@ ltq_etop_poll_rx(struct napi_struct *nap168 @@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) 160 169 } 161 170 if (complete || !rx) { … … 167 176 return rx; 168 177 } 169 @@ -185,12 +24 0,14 @@ ltq_etop_poll_tx(struct napi_struct *nap178 @@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) 170 179 container_of(napi, struct ltq_etop_chan, napi); 171 180 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); … … 183 192 ch->skb[ch->tx_free] = NULL; 184 193 memset(&ch->dma.desc_base[ch->tx_free], 0, 185 @@ -203,7 +26 0,9 @@ ltq_etop_poll_tx(struct napi_struct *nap194 @@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) 186 195 if (netif_tx_queue_stopped(txq)) 187 196 netif_tx_start_queue(txq); … … 193 202 } 194 203 195 @@ -211,9 +27 0,10 @@ static irqreturn_t204 @@ -211,9 +275,10 @@ static irqreturn_t 196 205 ltq_etop_dma_irq(int irq, void *_priv) 197 206 { … … 207 216 } 208 217 209 @@ -225,7 +2 85,7 @@ ltq_etop_free_channel(struct net_device218 @@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 210 219 ltq_dma_free(&ch->dma); 211 220 if (ch->dma.irq) … … 216 225 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 217 226 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 218 @@ -236,23 + 296,55@@ static void227 @@ -236,23 +301,59 @@ static void 219 228 ltq_etop_hw_exit(struct net_device *dev) 220 229 { … … 258 267 + replace default IPG value with 0x3B */ 259 268 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); 269 + /* set mdc clock to 2.5 MHz */ 270 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, 271 + LTQ_GBIT_RGMII_CTL); 260 272 } 261 273 … … 265 277 struct ltq_etop_priv *priv = netdev_priv(dev); 266 278 - int i; 279 + int mii_mode = priv->mii_mode; 280 + 281 + clk_enable(priv->clk_ppe); 267 282 268 283 - ltq_pmu_enable(PMU_PPE); 269 + clk_enable(priv->clk_ppe);270 +271 284 + if (of_machine_is_compatible("lantiq,ar9")) { 272 285 + ltq_etop_gbit_init(dev); 273 286 + /* force the etops link to the gbit to MII */ 274 + priv->mii_mode = PHY_INTERFACE_MODE_MII;287 + mii_mode = PHY_INTERFACE_MODE_MII; 275 288 + } 276 289 277 290 - switch (priv->pldata->mii_mode) { 278 + switch ( priv->mii_mode) {291 + switch (mii_mode) { 279 292 case PHY_INTERFACE_MODE_RMII: 280 293 ltq_etop_w32_mask(ETOP_MII_MASK, 281 294 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 282 @@ -264,39 +3 56,68 @@ ltq_etop_hw_init(struct net_device *dev)295 @@ -264,39 +365,68 @@ ltq_etop_hw_init(struct net_device *dev) 283 296 break; 284 297 … … 298 311 netdev_err(dev, "unknown mii mode %d\n", 299 312 - priv->pldata->mii_mode); 300 + priv->mii_mode);313 + mii_mode); 301 314 return -ENOTSUPP; 302 315 } … … 371 384 372 385 static void 373 @@ -312,7 +4 33,10 @@ ltq_etop_get_settings(struct net_device386 @@ -312,7 +442,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 374 387 { 375 388 struct ltq_etop_priv *priv = netdev_priv(dev); … … 383 396 384 397 static int 385 @@ -320,7 +4 44,10 @@ ltq_etop_set_settings(struct net_device398 @@ -320,7 +453,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 386 399 { 387 400 struct ltq_etop_priv *priv = netdev_priv(dev); … … 395 408 396 409 static int 397 @@ -328,7 +4 55,10 @@ ltq_etop_nway_reset(struct net_device *d410 @@ -328,7 +464,10 @@ ltq_etop_nway_reset(struct net_device *dev) 398 411 { 399 412 struct ltq_etop_priv *priv = netdev_priv(dev); … … 407 420 408 421 static const struct ethtool_ops ltq_etop_ethtool_ops = { 409 @@ -339,6 +4 69,39 @@ static const struct ethtool_ops ltq_etop422 @@ -339,6 +478,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = { 410 423 }; 411 424 … … 447 460 { 448 461 u32 val = MDIO_REQUEST | 449 @@ -379,14 +5 42,11 @@ ltq_etop_mdio_probe(struct net_device *d462 @@ -379,14 +551,18 @@ ltq_etop_mdio_probe(struct net_device *dev) 450 463 { 451 464 struct ltq_etop_priv *priv = netdev_priv(dev); 452 465 struct phy_device *phydev = NULL; 453 466 - int phy_addr; 454 467 - 455 468 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 456 469 - if (priv->mii_bus->phy_map[phy_addr]) { … … 459 472 - } 460 473 - } 474 + u32 phy_supported = (SUPPORTED_10baseT_Half 475 + | SUPPORTED_10baseT_Full 476 + | SUPPORTED_100baseT_Half 477 + | SUPPORTED_100baseT_Full 478 + | SUPPORTED_Autoneg 479 + | SUPPORTED_MII 480 + | SUPPORTED_TP); 481 + 461 482 + if (of_machine_is_compatible("lantiq,ase")) 462 483 + phydev = priv->mii_bus->phy_map[8]; … … 466 487 if (!phydev) { 467 488 netdev_err(dev, "no PHY found\n"); 468 @@ -394, 7 +554,7 @@ ltq_etop_mdio_probe(struct net_device *d489 @@ -394,21 +570,18 @@ ltq_etop_mdio_probe(struct net_device *dev) 469 490 } 470 491 … … 475 496 if (IS_ERR(phydev)) { 476 497 netdev_err(dev, "Could not attach to PHY\n"); 477 @@ -408,6 +568,9 @@ ltq_etop_mdio_probe(struct net_device *d 478 | SUPPORTED_Autoneg 479 | SUPPORTED_MII 480 | SUPPORTED_TP); 498 return PTR_ERR(phydev); 499 } 500 501 - phydev->supported &= (SUPPORTED_10baseT_Half 502 - | SUPPORTED_10baseT_Full 503 - | SUPPORTED_100baseT_Half 504 - | SUPPORTED_100baseT_Full 505 - | SUPPORTED_Autoneg 506 - | SUPPORTED_MII 507 - | SUPPORTED_TP); 481 508 + if (of_machine_is_compatible("lantiq,ar9")) 482 + phydev->supported &= SUPPORTED_1000baseT_Half 483 + | SUPPORTED_1000baseT_Full; 484 509 + phy_supported |= SUPPORTED_1000baseT_Half 510 + | SUPPORTED_1000baseT_Full; 511 512 + phydev->supported &= phy_supported; 485 513 phydev->advertising = phydev->supported; 486 514 priv->phydev = phydev; 487 @@ -433,8 +596,13 @@ ltq_etop_mdio_init(struct net_device *de 515 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", 516 @@ -433,8 +606,13 @@ ltq_etop_mdio_init(struct net_device *dev) 488 517 } 489 518 … … 501 530 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 502 531 priv->pdev->name, priv->pdev->id); 503 @@ -483,17 +6 51,19 @@ static int532 @@ -483,17 +661,19 @@ static int 504 533 ltq_etop_open(struct net_device *dev) 505 534 { … … 530 559 return 0; 531 560 } 532 @@ -502,18 +6 72,19 @@ static int561 @@ -502,18 +682,19 @@ static int 533 562 ltq_etop_stop(struct net_device *dev) 534 563 { … … 541 570 - for (i = 0; i < MAX_DMA_CHAN; i++) { 542 571 - struct ltq_etop_chan *ch = &priv->ch[i]; 543 - 572 + if (priv->phydev) 573 + phy_stop(priv->phydev); 574 + napi_disable(&priv->txch.napi); 575 + napi_disable(&priv->rxch.napi); 576 + 577 + spin_lock_irqsave(&priv->lock, flags); 578 + ltq_dma_close(&priv->txch.dma); 579 + ltq_dma_close(&priv->rxch.dma); 580 + spin_unlock_irqrestore(&priv->lock, flags); 581 544 582 - if (!IS_RX(i) && !IS_TX(i)) 545 583 - continue; … … 547 585 - ltq_dma_close(&ch->dma); 548 586 - } 549 + if (priv->phydev)550 + phy_stop(priv->phydev);551 + napi_disable(&priv->txch.napi);552 + napi_disable(&priv->rxch.napi);553 +554 + spin_lock_irqsave(&priv->lock, flags);555 + ltq_dma_close(&priv->txch.dma);556 + ltq_dma_close(&priv->rxch.dma);557 + spin_unlock_irqrestore(&priv->lock, flags);558 +559 587 return 0; 560 588 } 561 589 562 @@ -523,16 + 694,16 @@ ltq_etop_tx(struct sk_buff *skb, struct590 @@ -523,16 +704,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 563 591 int queue = skb_get_queue_mapping(skb); 564 592 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); … … 582 610 netif_tx_stop_queue(txq); 583 611 return NETDEV_TX_BUSY; 584 @@ -540,7 +7 11,7 @@ ltq_etop_tx(struct sk_buff *skb, struct612 @@ -540,7 +721,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 585 613 586 614 /* dma needs to start on a 16 byte aligned address */ … … 591 619 dev->trans_start = jiffies; 592 620 593 @@ -550,11 +7 21,11 @@ ltq_etop_tx(struct sk_buff *skb, struct621 @@ -550,11 +731,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 594 622 wmb(); 595 623 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | … … 606 634 607 635 return NETDEV_TX_OK; 608 @@ -633,34 +8 04,32 @@ ltq_etop_init(struct net_device *dev)636 @@ -633,34 +814,32 @@ ltq_etop_init(struct net_device *dev) 609 637 struct ltq_etop_priv *priv = netdev_priv(dev); 610 638 struct sockaddr mac; … … 651 679 652 680 err_netdev: 653 @@ -680,6 +8 49,9 @@ ltq_etop_tx_timeout(struct net_device *d681 @@ -680,6 +859,9 @@ ltq_etop_tx_timeout(struct net_device *dev) 654 682 err = ltq_etop_hw_init(dev); 655 683 if (err) … … 661 689 netif_wake_queue(dev); 662 690 return; 663 @@ -703,14 +8 75,19 @@ static const struct net_device_ops ltq_e691 @@ -703,14 +885,19 @@ static const struct net_device_ops ltq_eth_netdev_ops = { 664 692 .ndo_tx_timeout = ltq_etop_tx_timeout, 665 693 }; … … 684 712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 685 713 if (!res) { 686 @@ -736,30 +9 13,58 @@ ltq_etop_probe(struct platform_device *p714 @@ -736,30 +923,58 @@ ltq_etop_probe(struct platform_device *pdev) 687 715 goto err_out; 688 716 } … … 758 786 err = register_netdev(dev); 759 787 if (err) 760 @@ -788,32 + 993,23 @@ ltq_etop_remove(struct platform_device *788 @@ -788,32 +1003,23 @@ ltq_etop_remove(struct platform_device *pdev) 761 789 return 0; 762 790 } … … 770 798 static struct platform_driver ltq_mii_driver = { 771 799 + .probe = ltq_etop_probe, 772 .remove = __devexit_p(ltq_etop_remove),800 .remove = ltq_etop_remove, 773 801 .driver = { 774 802 .name = "ltq_etop", … … 800 828 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 801 829 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 830 -- 831 1.7.10.4 832 -
trunk/target/linux/lantiq/patches-3.8/0027-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
r36013 r36014 1 From 12f4b99d63edc15849357c09e22a36445c2752ccMon Sep 17 00:00:00 20011 From 0721e9f0502e633390044e651970692213283686 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Mon, 22 Oct 2012 09:28:30 +02004 Subject: [PATCH 115/123] NET: PHY: adds driver for lantiq PHY11G3 Date: Wed, 13 Mar 2013 09:30:22 +0100 4 Subject: [PATCH 27/40] NET: PHY: adds driver for lantiq PHY11G 5 5 6 6 Signed-off-by: John Crispin <blogic@openwrt.org> … … 8 8 drivers/net/phy/Kconfig | 5 ++ 9 9 drivers/net/phy/Makefile | 1 + 10 drivers/net/phy/lantiq.c | 178++++++++++++++++++++++++++++++++++++++++++++++11 3 files changed, 184insertions(+)10 drivers/net/phy/lantiq.c | 220 ++++++++++++++++++++++++++++++++++++++++++++++ 11 3 files changed, 226 insertions(+) 12 12 create mode 100644 drivers/net/phy/lantiq.c 13 13 14 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig 15 index 961f0b2..41a2992 100644 14 16 --- a/drivers/net/phy/Kconfig 15 17 +++ b/drivers/net/phy/Kconfig 16 @@ -1 50,6 +150,11 @@ config MICREL_PHY18 @@ -107,6 +107,11 @@ config MICREL_PHY 17 19 ---help--- 18 Currently has a driver for the KSZ804120 Supports the KSZ9021, VSC8201, KS8001 PHYs. 19 21 20 22 +config LANTIQ_PHY … … 26 28 bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" 27 29 depends on PHYLIB=y 30 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile 31 index 9645e38..e2eeee3 100644 28 32 --- a/drivers/net/phy/Makefile 29 33 +++ b/drivers/net/phy/Makefile 30 @@ - 39,6 +39,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o34 @@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o 31 35 obj-$(CONFIG_DP83640_PHY) += dp83640.o 32 36 obj-$(CONFIG_STE10XP) += ste10Xp.o … … 36 40 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o 37 41 obj-$(CONFIG_AT803X_PHY) += at803x.o 42 diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c 43 new file mode 100644 44 index 0000000..418dff0 38 45 --- /dev/null 39 46 +++ b/drivers/net/phy/lantiq.c … … 259 266 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>"); 260 267 +MODULE_LICENSE("GPL"); 268 -- 269 1.7.10.4 270 -
trunk/target/linux/lantiq/patches-3.8/0028-NET-lantiq-adds-PHY11G-firmware-blobs.patch
r36013 r36014 1 From 870dad40d334e9e8342f28dbcad1410cad12a945Mon Sep 17 00:00:00 20011 From 9664031d0f35be450330bf30ded1c359b9074251 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Mon, 22 Oct 2012 09:26:24 +0200 4 Subject: [PATCH 118/123] owrt: adds PHY11G firmware blobs4 Subject: [PATCH 28/40] NET: lantiq: adds PHY11G firmware blobs 5 5 6 6 Signed-off-by: John Crispin <blogic@openwrt.org> 7 7 --- 8 firmware/Makefile | 1 + 9 firmware/lantiq/COPYING | 286 ++++++++++++++++++++++++++++++++++++ 10 firmware/lantiq/README | 45 ++++++ 11 firmware/lantiq/vr9_phy11g_a1x.bin | Bin 0 -> 65536 bytes 12 firmware/lantiq/vr9_phy11g_a2x.bin | Bin 0 -> 65536 bytes 13 firmware/lantiq/vr9_phy22f_a1x.bin | Bin 0 -> 65536 bytes 14 firmware/lantiq/vr9_phy22f_a2x.bin | Bin 0 -> 65536 bytes 15 7 files changed, 332 insertions(+) 8 firmware/Makefile | 2 + 9 firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++ 10 firmware/lantiq/README | 45 ++++++++ 11 3 files changed, 333 insertions(+) 16 12 create mode 100644 firmware/lantiq/COPYING 17 13 create mode 100644 firmware/lantiq/README 18 create mode 100644 firmware/lantiq/vr9_phy11g_a1x.bin 19 create mode 100644 firmware/lantiq/vr9_phy11g_a2x.bin 20 create mode 100644 firmware/lantiq/vr9_phy22f_a1x.bin 21 create mode 100644 firmware/lantiq/vr9_phy22f_a2x.bin 22 14 15 diff --git a/firmware/Makefile b/firmware/Makefile 16 index cbb09ce..cdc0aef 100644 23 17 --- a/firmware/Makefile 24 18 +++ b/firmware/Makefile 25 @@ -13 5,6 +135,8 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P19 @@ -134,6 +134,8 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw 26 20 fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw 27 21 fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw … … 32 26 33 27 fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) 28 diff --git a/firmware/lantiq/COPYING b/firmware/lantiq/COPYING 29 new file mode 100644 30 index 0000000..5ec70b2 34 31 --- /dev/null 35 32 +++ b/firmware/lantiq/COPYING … … 325 322 + 326 323 + END OF TERMS AND CONDITIONS 324 diff --git a/firmware/lantiq/README b/firmware/lantiq/README 325 new file mode 100644 326 index 0000000..cb1a10a 327 327 --- /dev/null 328 328 +++ b/firmware/lantiq/README … … 373 373 +lantiq/vr9_phy11g_a2x.bin 374 374 +lantiq/vr9_phy22f_a2x.bin 375 -- 376 1.7.10.4 377 -
trunk/target/linux/lantiq/patches-3.8/0030-MIPS-lantiq-add-pcie-driver.patch
r36013 r36014 1 From b0b68cd5b5da72950863af882c368f28f65690e8Mon Sep 17 00:00:00 20011 From 86b0b37729298b067157263b7bf5dbf735527e7c Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Thu, 6 Dec 2012 11:43:53+01004 Subject: [PATCH 122/123] MIPS: lantiq: addspcie driver3 Date: Wed, 13 Mar 2013 09:39:02 +0100 4 Subject: [PATCH 30/40] MIPS: lantiq: add pcie driver 5 5 6 6 --- … … 26 26 19 files changed, 4576 insertions(+), 1 deletion(-) 27 27 create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c 28 create mode 100 755arch/mips/pci/ifxmips_pci_common.h28 create mode 100644 arch/mips/pci/ifxmips_pci_common.h 29 29 create mode 100644 arch/mips/pci/ifxmips_pcie.c 30 30 create mode 100644 arch/mips/pci/ifxmips_pcie.h … … 37 37 create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h 38 38 39 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig 40 index 675310a..4c9a241 100644 39 41 --- a/arch/mips/lantiq/Kconfig 40 42 +++ b/arch/mips/lantiq/Kconfig 41 @@ -1 7,6 +17,7 @@ config SOC_XWAY43 @@ -18,6 +18,7 @@ config SOC_XWAY 42 44 bool "XWAY" 43 45 select SOC_TYPE_XWAY … … 47 49 config SOC_FALCON 48 50 bool "FALCON" 49 @@ - 40,6 +41,15 @@ config PCI_LANTIQ51 @@ -37,6 +38,15 @@ config PCI_LANTIQ 50 52 bool "PCI Support" 51 53 depends on SOC_XWAY && PCI … … 63 65 bool "XRX200 PHY firmware loader" 64 66 depends on SOC_XWAY 67 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c 68 index c24924f..e30dde8 100644 65 69 --- a/arch/mips/lantiq/xway/sysctrl.c 66 70 +++ b/arch/mips/lantiq/xway/sysctrl.c … … 74 78 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 75 79 ltq_ar9_fpi_hz(), CLOCK_250M); 80 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile 81 index ce995d3..bd32fe1 100644 76 82 --- a/arch/mips/pci/Makefile 77 83 +++ b/arch/mips/pci/Makefile 78 @@ -4 4,6 +44,8 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm184 @@ -42,6 +42,8 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o 79 85 obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o 80 86 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o … … 85 91 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 86 92 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 93 diff --git a/arch/mips/pci/fixup-lantiq-pcie.c b/arch/mips/pci/fixup-lantiq-pcie.c 94 new file mode 100644 95 index 0000000..50a1c3b 87 96 --- /dev/null 88 97 +++ b/arch/mips/pci/fixup-lantiq-pcie.c … … 170 179 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, 171 180 + ifx_pcie_rc_class_early_fixup); 181 diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c 182 index 6c829df..cf5c4e0 100644 172 183 --- a/arch/mips/pci/fixup-lantiq.c 173 184 +++ b/arch/mips/pci/fixup-lantiq.c … … 180 191 int pcibios_plat_dev_init(struct pci_dev *dev) 181 192 { 182 @@ -28,6 +29,8 @@ int __init pcibios_map_irq(const struct 193 @@ -28,6 +29,8 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 183 194 struct of_irq dev_irq; 184 195 int irq; … … 189 200 dev_err(&dev->dev, "trying to map irq for unknown slot:%d pin:%d\n", 190 201 slot, pin); 202 diff --git a/arch/mips/pci/ifxmips_pci_common.h b/arch/mips/pci/ifxmips_pci_common.h 203 new file mode 100644 204 index 0000000..46f4cb2 191 205 --- /dev/null 192 206 +++ b/arch/mips/pci/ifxmips_pci_common.h … … 249 263 +#endif /* IFXMIPS_PCI_COMMON_H */ 250 264 + 265 diff --git a/arch/mips/pci/ifxmips_pcie.c b/arch/mips/pci/ifxmips_pcie.c 266 new file mode 100644 267 index 0000000..5cebfe6 251 268 --- /dev/null 252 269 +++ b/arch/mips/pci/ifxmips_pcie.c … … 1859 1876 +MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); 1860 1877 + 1878 diff --git a/arch/mips/pci/ifxmips_pcie.h b/arch/mips/pci/ifxmips_pcie.h 1879 new file mode 100644 1880 index 0000000..c6f92f5 1861 1881 --- /dev/null 1862 1882 +++ b/arch/mips/pci/ifxmips_pcie.h … … 1997 2017 +#endif /* IFXMIPS_PCIE_H */ 1998 2018 + 2019 diff --git a/arch/mips/pci/ifxmips_pcie_ar10.h b/arch/mips/pci/ifxmips_pcie_ar10.h 2020 new file mode 100644 2021 index 0000000..99ff463 1999 2022 --- /dev/null 2000 2023 +++ b/arch/mips/pci/ifxmips_pcie_ar10.h … … 2290 2313 + 2291 2314 +#endif /* IFXMIPS_PCIE_AR10_H */ 2315 diff --git a/arch/mips/pci/ifxmips_pcie_msi.c b/arch/mips/pci/ifxmips_pcie_msi.c 2316 new file mode 100644 2317 index 0000000..bffd6fa 2292 2318 --- /dev/null 2293 2319 +++ b/arch/mips/pci/ifxmips_pcie_msi.c … … 2685 2711 +MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); 2686 2712 + 2713 diff --git a/arch/mips/pci/ifxmips_pcie_phy.c b/arch/mips/pci/ifxmips_pcie_phy.c 2714 new file mode 100644 2715 index 0000000..f5b0f13 2687 2716 --- /dev/null 2688 2717 +++ b/arch/mips/pci/ifxmips_pcie_phy.c … … 3166 3195 +} 3167 3196 + 3197 diff --git a/arch/mips/pci/ifxmips_pcie_pm.c b/arch/mips/pci/ifxmips_pcie_pm.c 3198 new file mode 100644 3199 index 0000000..a10ecad 3168 3200 --- /dev/null 3169 3201 +++ b/arch/mips/pci/ifxmips_pcie_pm.c … … 3345 3377 +} 3346 3378 + 3379 diff --git a/arch/mips/pci/ifxmips_pcie_pm.h b/arch/mips/pci/ifxmips_pcie_pm.h 3380 new file mode 100644 3381 index 0000000..6ece20d 3347 3382 --- /dev/null 3348 3383 +++ b/arch/mips/pci/ifxmips_pcie_pm.h … … 3384 3419 +#endif /* IFXMIPS_PCIE_PM_H */ 3385 3420 + 3421 diff --git a/arch/mips/pci/ifxmips_pcie_reg.h b/arch/mips/pci/ifxmips_pcie_reg.h 3422 new file mode 100644 3423 index 0000000..e7e4b6c 3386 3424 --- /dev/null 3387 3425 +++ b/arch/mips/pci/ifxmips_pcie_reg.h … … 4388 4426 +#endif /* IFXMIPS_PCIE_REG_H */ 4389 4427 + 4428 diff --git a/arch/mips/pci/ifxmips_pcie_vr9.h b/arch/mips/pci/ifxmips_pcie_vr9.h 4429 new file mode 100644 4430 index 0000000..57d9368 4390 4431 --- /dev/null 4391 4432 +++ b/arch/mips/pci/ifxmips_pcie_vr9.h … … 4662 4703 +#endif /* IFXMIPS_PCIE_VR9_H */ 4663 4704 + 4705 diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c 4706 index a184344..35ca57f 100644 4664 4707 --- a/arch/mips/pci/pci.c 4665 4708 +++ b/arch/mips/pci/pci.c 4666 @@ -2 50,6 +250,31 @@ static int __init pcibios_init(void)4709 @@ -249,6 +249,31 @@ static int __init pcibios_init(void) 4667 4710 4668 4711 subsys_initcall(pcibios_init); … … 4696 4739 { 4697 4740 u16 cmd, old_cmd; 4741 diff --git a/drivers/pci/pcie/aer/Kconfig b/drivers/pci/pcie/aer/Kconfig 4742 index 50e94e0..4bf848f 100644 4698 4743 --- a/drivers/pci/pcie/aer/Kconfig 4699 4744 +++ b/drivers/pci/pcie/aer/Kconfig … … 4707 4752 This enables PCI Express Root Port Advanced Error Reporting 4708 4753 (AER) driver support. Error reporting messages sent to Root 4754 diff --git a/include/linux/pci.h b/include/linux/pci.h 4755 index 15472d6..73b6926 100644 4709 4756 --- a/include/linux/pci.h 4710 4757 +++ b/include/linux/pci.h 4711 @@ -10 38,6 +1038,8 @@ void pci_walk_bus(struct pci_bus *top, i4758 @@ -1059,6 +1059,8 @@ void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 4712 4759 int pci_cfg_space_size_ext(struct pci_dev *dev); 4713 4760 int pci_cfg_space_size(struct pci_dev *dev); … … 4718 4765 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 4719 4766 unsigned long type); 4767 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h 4768 index 0eb6579..81adb58 100644 4720 4769 --- a/include/linux/pci_ids.h 4721 4770 +++ b/include/linux/pci_ids.h … … 4733 4782 #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 4734 4783 #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 4784 -- 4785 1.7.10.4 4786 -
trunk/target/linux/lantiq/patches-3.8/0031-MIPS-lantiq-adds-minimal-dcdc-driver.patch
r36013 r36014 1 From 3aa46ed76b27df771f75db9c74ff011aca505fc5Mon Sep 17 00:00:00 20011 From 1f95983593d5b6634c13ead8f923237484dc611e Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Wed, 5 Dec 2012 17:38:48 +0100 4 Subject: [PATCH 106/123] MIPS: lantiq: adds minimal dcdc driver4 Subject: [PATCH 31/40] MIPS: lantiq: adds minimal dcdc driver 5 5 6 6 This driver so far only reads the core voltage. … … 13 13 create mode 100644 arch/mips/lantiq/xway/dcdc.c 14 14 15 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile 16 index 7a13660..087497d 100644 15 17 --- a/arch/mips/lantiq/xway/Makefile 16 18 +++ b/arch/mips/lantiq/xway/Makefile … … 20 22 21 23 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o 24 diff --git a/arch/mips/lantiq/xway/dcdc.c b/arch/mips/lantiq/xway/dcdc.c 25 new file mode 100644 26 index 0000000..8dd871a 22 27 --- /dev/null 23 28 +++ b/arch/mips/lantiq/xway/dcdc.c … … 50 55 +static void __iomem *dcdc_membase; 51 56 + 52 +static int __devinitdcdc_probe(struct platform_device *pdev)57 +static int dcdc_probe(struct platform_device *pdev) 53 58 +{ 54 59 + struct resource *res; … … 97 102 + 98 103 +arch_initcall(dcdc_init); 104 -- 105 1.7.10.4 106 -
trunk/target/linux/lantiq/patches-3.8/0032-MTD-lantiq-Add-NAND-support-on-Lantiq-Falcon-SoC.patch
r36013 r36014 1 From 72112b91624dca6c636bd3a592471642d3988b27Mon Sep 17 00:00:00 20011 From 2fd60458657ac96ab71ba4831cfb397145b3c989 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Fri, 20 Jul 2012 19:09:01 +0200 4 Subject: [PATCH 111/123] MTD: MIPS: lantiq: Add NAND support on Lantiq FALCON 5 SoC. 3 Date: Wed, 30 Jan 2013 21:12:47 +0100 4 Subject: [PATCH 32/40] MTD: lantiq: Add NAND support on Lantiq Falcon SoC. 6 5 7 6 The driver uses plat_nand. As the platform_device is loaded from DT, we need 8 to lookup the node and attach our fal ocn specific "struct platform_nand_data"7 to lookup the node and attach our falcon specific "struct platform_nand_data" 9 8 to it. 10 9 10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> 11 11 Signed-off-by: John Crispin <blogic@openwrt.org> 12 Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>13 Cc: linux-mtd@lists.infradead.org14 12 --- 15 13 drivers/mtd/nand/Kconfig | 8 ++++ 16 14 drivers/mtd/nand/Makefile | 1 + 17 drivers/mtd/nand/falcon_nand.c | 8 2++++++++++++++++++++++++++++++++++++++++18 3 files changed, 9 1insertions(+)15 drivers/mtd/nand/falcon_nand.c | 83 ++++++++++++++++++++++++++++++++++++++++ 16 3 files changed, 92 insertions(+) 19 17 create mode 100644 drivers/mtd/nand/falcon_nand.c 20 18 19 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig 20 index 5819eb5..058939d 100644 21 21 --- a/drivers/mtd/nand/Kconfig 22 22 +++ b/drivers/mtd/nand/Kconfig 23 @@ -57 2,4 +572,12 @@ config MTD_NAND_XWAY23 @@ -575,4 +575,12 @@ config MTD_NAND_XWAY 24 24 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached 25 25 to the External Bus Unit (EBU). … … 34 34 + 35 35 endif # MTD_NAND 36 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile 37 index d76d912..1a61bf0 100644 36 38 --- a/drivers/mtd/nand/Makefile 37 39 +++ b/drivers/mtd/nand/Makefile 38 @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_RICOH) += r852.o 39 obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o 40 @@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o 40 41 obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ 41 42 obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o 43 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ 42 44 +obj-$(CONFIG_MTD_NAND_FALCON) += falcon_nand.o 43 45 44 46 nand-objs := nand_base.o nand_bbt.o 47 diff --git a/drivers/mtd/nand/falcon_nand.c b/drivers/mtd/nand/falcon_nand.c 48 new file mode 100644 49 index 0000000..13458d3 45 50 --- /dev/null 46 51 +++ b/drivers/mtd/nand/falcon_nand.c 47 @@ -0,0 +1,8 2@@52 @@ -0,0 +1,83 @@ 48 53 +/* 49 54 + * This program is free software; you can redistribute it and/or modify it … … 60 65 +#include <lantiq_soc.h> 61 66 + 62 +/* nand flash */63 67 +/* address lines used for NAND control signals */ 64 68 +#define NAND_ADDR_ALE 0x10000 65 69 +#define NAND_ADDR_CLE 0x20000 70 + 66 71 +/* Ready/Busy Status */ 67 72 +#define MODCON_STS 0x0002 73 + 68 74 +/* Ready/Busy Status Edge */ 69 75 +#define MODCON_STSEDGE 0x0004 70 76 +#define LTQ_EBU_MODCON 0x000C 71 77 + 72 +static const char *part_probes[] = { "cmdlinepart", "ofpart", NULL };78 +static const char const *part_probes[] = { "cmdlinepart", "ofpart", NULL }; 73 79 + 74 80 +static int falcon_nand_ready(struct mtd_info *mtd) … … 112 118 +}; 113 119 + 114 + staticint __init falcon_register_nand(void)120 +int __init falcon_register_nand(void) 115 121 +{ 116 122 + struct device_node *node; … … 128 134 + 129 135 +arch_initcall(falcon_register_nand); 136 -- 137 1.7.10.4 138 -
trunk/target/linux/lantiq/patches-3.8/0036-owrt-lantiq-dtb-image-hack.patch
r36013 r36014 1 From d8f83a608bc854dbbe6b2ea5436e9b34516af8e4Mon Sep 17 00:00:00 20011 From 5128799df668a7ff5b2861fab39f9f788369eb43 Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 Date: Thu, 6 Dec 2012 16:09:08+01004 Subject: [PATCH 121/123] owrt: lantiq dtb image hack3 Date: Wed, 13 Mar 2013 09:36:16 +0100 4 Subject: [PATCH 36/40] owrt: lantiq dtb image hack 5 5 6 6 --- 7 arch/mips/lantiq/prom.c | 4 +++- 8 1 file changed, 3 insertions(+), 1 deletion(-) 7 arch/mips/lantiq/Makefile | 2 -- 8 arch/mips/lantiq/prom.c | 4 +++- 9 2 files changed, 3 insertions(+), 3 deletions(-) 9 10 10 --- a/arch/mips/lantiq/prom.c 11 +++ b/arch/mips/lantiq/prom.c 12 @@ -72,6 +72,8 @@ int __init early_init_dt_scan_model(unsi 13 return 0; 14 } 15 16 +extern struct boot_param_header __image_dtb; 17 + 18 void __init plat_mem_setup(void) 19 { 20 ioport_resource.start = IOPORT_RESOURCE_START; 21 @@ -85,7 +87,7 @@ void __init plat_mem_setup(void) 22 * Load the builtin devicetree. This causes the chosen node to be 23 * parsed resulting in our memory appearing 24 */ 25 - __dt_setup_arch(&__dtb_start); 26 + __dt_setup_arch(&__image_dtb); 27 28 of_scan_flat_dt(early_init_dt_scan_model, NULL); 29 } 11 diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile 12 index d6bdc57..690257a 100644 30 13 --- a/arch/mips/lantiq/Makefile 31 14 +++ b/arch/mips/lantiq/Makefile … … 39 22 40 23 obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ 24 diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c 25 index 9f9e875..72b183a 100644 26 --- a/arch/mips/lantiq/prom.c 27 +++ b/arch/mips/lantiq/prom.c 28 @@ -57,6 +57,8 @@ static void __init prom_init_cmdline(void) 29 } 30 } 31 32 +extern struct boot_param_header __image_dtb; 33 + 34 void __init plat_mem_setup(void) 35 { 36 ioport_resource.start = IOPORT_RESOURCE_START; 37 @@ -70,7 +72,7 @@ void __init plat_mem_setup(void) 38 * Load the builtin devicetree. This causes the chosen node to be 39 * parsed resulting in our memory appearing 40 */ 41 - __dt_setup_arch(&__dtb_start); 42 + __dt_setup_arch(&__image_dtb); 43 } 44 45 void __init device_tree_init(void) 46 -- 47 1.7.10.4 48 -
trunk/target/linux/lantiq/patches-3.8/0037-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
r36013 r36014 1 From 0c9b05716ac0e597ae0f81a96ff68e54716decc9 Mon Sep 17 00:00:00 2001 2 From: John Crispin <blogic@openwrt.org> 3 Date: Wed, 13 Mar 2013 10:02:58 +0100 4 Subject: [PATCH 37/40] owrt: lantiq: wifi and ethernet eeprom handling 5 6 --- 7 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 + 8 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + 9 arch/mips/lantiq/xway/Makefile | 3 + 10 arch/mips/lantiq/xway/ath_eep.c | 206 ++++++++++++++++++++ 11 arch/mips/lantiq/xway/eth_mac.c | 76 ++++++++ 12 arch/mips/lantiq/xway/pci-ath-fixup.c | 109 +++++++++++ 13 arch/mips/lantiq/xway/rt_eep.c | 60 ++++++ 14 drivers/net/ethernet/lantiq_etop.c | 10 +- 15 8 files changed, 469 insertions(+), 4 deletions(-) 16 create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 17 create mode 100644 arch/mips/lantiq/xway/ath_eep.c 18 create mode 100644 arch/mips/lantiq/xway/eth_mac.c 19 create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c 20 create mode 100644 arch/mips/lantiq/xway/rt_eep.c 21 22 diff --git a/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 23 new file mode 100644 24 index 0000000..095d2619 25 --- /dev/null 26 +++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 27 @@ -0,0 +1,6 @@ 28 +#ifndef _PCI_ATH_FIXUP 29 +#define _PCI_ATH_FIXUP 30 + 31 +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; 32 + 33 +#endif /* _PCI_ATH_FIXUP */ 34 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 35 index 133336b..779715c 100644 36 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 37 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 38 @@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr); 39 extern void ltq_pmu_enable(unsigned int module); 40 extern void ltq_pmu_disable(unsigned int module); 41 42 +/* allow the ethernet driver to load a flash mapped mac addr */ 43 +const u8* ltq_get_eth_mac(void); 44 + 45 #endif /* CONFIG_SOC_TYPE_XWAY */ 46 #endif /* _LTQ_XWAY_H__ */ 47 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile 48 index 087497d..51f0eba 100644 1 49 --- a/arch/mips/lantiq/xway/Makefile 2 50 +++ b/arch/mips/lantiq/xway/Makefile 3 51 @@ -1,3 +1,6 @@ 4 obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o52 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o 5 53 6 54 +obj-y += eth_mac.o … … 8 56 + 9 57 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o 58 diff --git a/arch/mips/lantiq/xway/ath_eep.c b/arch/mips/lantiq/xway/ath_eep.c 59 new file mode 100644 60 index 0000000..96da7c1 10 61 --- /dev/null 11 62 +++ b/arch/mips/lantiq/xway/ath_eep.c … … 217 268 +} 218 269 +device_initcall(of_ath5k_eeprom_init); 219 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 220 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 221 @@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, 222 extern void ltq_pmu_enable(unsigned int module); 223 extern void ltq_pmu_disable(unsigned int module); 224 225 +/* allow the ethernet driver to load a flash mapped mac addr */ 226 +const u8* ltq_get_eth_mac(void); 227 + 228 #endif /* CONFIG_SOC_TYPE_XWAY */ 229 #endif /* _LTQ_XWAY_H__ */ 270 diff --git a/arch/mips/lantiq/xway/eth_mac.c b/arch/mips/lantiq/xway/eth_mac.c 271 new file mode 100644 272 index 0000000..d288a0e 230 273 --- /dev/null 231 274 +++ b/arch/mips/lantiq/xway/eth_mac.c … … 307 350 +} 308 351 +device_initcall(of_eth_mac_init); 309 --- a/drivers/net/ethernet/lantiq_etop.c 310 +++ b/drivers/net/ethernet/lantiq_etop.c 311 @@ -825,7 +825,8 @@ ltq_etop_init(struct net_device *dev) 312 313 ltq_etop_change_mtu(dev, 1500); 314 315 - memcpy(&mac.sa_data, priv->mac, ETH_ALEN); 316 + if (priv->mac) 317 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN); 318 if (!is_valid_ether_addr(mac.sa_data)) { 319 pr_warn("etop: invalid MAC, using random\n"); 320 random_ether_addr(mac.sa_data); 321 @@ -949,7 +950,9 @@ ltq_etop_probe(struct platform_device *p 322 priv->tx_irq = irqres[0].start; 323 priv->rx_irq = irqres[1].start; 324 priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); 325 - priv->mac = of_get_mac_address(pdev->dev.of_node); 326 + priv->mac = ltq_get_eth_mac(); 327 + if (!priv->mac) 328 + priv->mac = of_get_mac_address(pdev->dev.of_node); 329 330 priv->clk_ppe = clk_get(&pdev->dev, NULL); 331 if (IS_ERR(priv->clk_ppe)) 332 --- /dev/null 333 +++ b/arch/mips/lantiq/xway/rt_eep.c 334 @@ -0,0 +1,60 @@ 335 +/* 336 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 337 + * 338 + * This program is free software; you can redistribute it and/or modify it 339 + * under the terms of the GNU General Public License version 2 as published 340 + * by the Free Software Foundation. 341 + */ 342 + 343 +#include <linux/init.h> 344 +#include <linux/module.h> 345 +#include <linux/pci.h> 346 +#include <linux/platform_device.h> 347 +#include <linux/rt2x00_platform.h> 348 + 349 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); 350 +static struct rt2x00_platform_data rt2x00_pdata; 351 + 352 +static int rt2x00_pci_plat_dev_init(struct pci_dev *dev) 353 +{ 354 + dev->dev.platform_data = &rt2x00_pdata; 355 + return 0; 356 +} 357 + 358 +int __init of_ralink_eeprom_probe(struct platform_device *pdev) 359 +{ 360 + struct device_node *np = pdev->dev.of_node; 361 + const char *eeprom; 362 + 363 + if (of_property_read_string(np, "ralink,eeprom", &eeprom)) { 364 + dev_err(&pdev->dev, "failed to load eeprom filename\n"); 365 + return 0; 366 + } 367 + 368 + rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); 369 +// rt2x00_pdata.mac_address = mac; 370 + ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init; 371 + 372 + dev_info(&pdev->dev, "using %s as eeprom\n", eeprom); 373 + 374 + return 0; 375 +} 376 + 377 +static struct of_device_id ralink_eeprom_ids[] = { 378 + { .compatible = "ralink,eeprom" }, 379 + { } 380 +}; 381 + 382 +static struct platform_driver ralink_eeprom_driver = { 383 + .driver = { 384 + .name = "ralink,eeprom", 385 + .owner = THIS_MODULE, 386 + .of_match_table = of_match_ptr(ralink_eeprom_ids), 387 + }, 388 +}; 389 + 390 +static int __init of_ralink_eeprom_init(void) 391 +{ 392 + return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe); 393 +} 394 +device_initcall(of_ralink_eeprom_init); 395 --- /dev/null 396 +++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h 397 @@ -0,0 +1,6 @@ 398 +#ifndef _PCI_ATH_FIXUP 399 +#define _PCI_ATH_FIXUP 400 + 401 +void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; 402 + 403 +#endif /* _PCI_ATH_FIXUP */ 352 diff --git a/arch/mips/lantiq/xway/pci-ath-fixup.c b/arch/mips/lantiq/xway/pci-ath-fixup.c 353 new file mode 100644 354 index 0000000..c87ffb2 404 355 --- /dev/null 405 356 +++ b/arch/mips/lantiq/xway/pci-ath-fixup.c … … 514 465 + ath_num_fixups++; 515 466 +} 467 diff --git a/arch/mips/lantiq/xway/rt_eep.c b/arch/mips/lantiq/xway/rt_eep.c 468 new file mode 100644 469 index 0000000..00f2d4c 470 --- /dev/null 471 +++ b/arch/mips/lantiq/xway/rt_eep.c 472 @@ -0,0 +1,60 @@ 473 +/* 474 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 475 + * 476 + * This program is free software; you can redistribute it and/or modify it 477 + * under the terms of the GNU General Public License version 2 as published 478 + * by the Free Software Foundation. 479 + */ 480 + 481 +#include <linux/init.h> 482 +#include <linux/module.h> 483 +#include <linux/pci.h> 484 +#include <linux/platform_device.h> 485 +#include <linux/rt2x00_platform.h> 486 + 487 +extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); 488 +static struct rt2x00_platform_data rt2x00_pdata; 489 + 490 +static int rt2x00_pci_plat_dev_init(struct pci_dev *dev) 491 +{ 492 + dev->dev.platform_data = &rt2x00_pdata; 493 + return 0; 494 +} 495 + 496 +int __init of_ralink_eeprom_probe(struct platform_device *pdev) 497 +{ 498 + struct device_node *np = pdev->dev.of_node; 499 + const char *eeprom; 500 + 501 + if (of_property_read_string(np, "ralink,eeprom", &eeprom)) { 502 + dev_err(&pdev->dev, "failed to load eeprom filename\n"); 503 + return 0; 504 + } 505 + 506 + rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); 507 +// rt2x00_pdata.mac_address = mac; 508 + ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init; 509 + 510 + dev_info(&pdev->dev, "using %s as eeprom\n", eeprom); 511 + 512 + return 0; 513 +} 514 + 515 +static struct of_device_id ralink_eeprom_ids[] = { 516 + { .compatible = "ralink,eeprom" }, 517 + { } 518 +}; 519 + 520 +static struct platform_driver ralink_eeprom_driver = { 521 + .driver = { 522 + .name = "ralink,eeprom", 523 + .owner = THIS_MODULE, 524 + .of_match_table = of_match_ptr(ralink_eeprom_ids), 525 + }, 526 +}; 527 + 528 +static int __init of_ralink_eeprom_init(void) 529 +{ 530 + return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe); 531 +} 532 +device_initcall(of_ralink_eeprom_init); 533 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c 534 index 91a37f1..fa23a7e 100644 535 --- a/drivers/net/ethernet/lantiq_etop.c 536 +++ b/drivers/net/ethernet/lantiq_etop.c 537 @@ -826,7 +826,8 @@ ltq_etop_init(struct net_device *dev) 538 539 ltq_etop_change_mtu(dev, 1500); 540 541 - memcpy(&mac.sa_data, priv->mac, ETH_ALEN); 542 + if (priv->mac) 543 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN); 544 if (!is_valid_ether_addr(mac.sa_data)) { 545 pr_warn("etop: invalid MAC, using random\n"); 546 random_ether_addr(mac.sa_data); 547 @@ -885,8 +886,7 @@ static const struct net_device_ops ltq_eth_netdev_ops = { 548 .ndo_tx_timeout = ltq_etop_tx_timeout, 549 }; 550 551 -static int __devinit 552 -ltq_etop_probe(struct platform_device *pdev) 553 +static int ltq_etop_probe(struct platform_device *pdev) 554 { 555 struct net_device *dev; 556 struct ltq_etop_priv *priv; 557 @@ -950,7 +950,9 @@ ltq_etop_probe(struct platform_device *pdev) 558 priv->tx_irq = irqres[0].start; 559 priv->rx_irq = irqres[1].start; 560 priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); 561 - priv->mac = of_get_mac_address(pdev->dev.of_node); 562 + priv->mac = ltq_get_eth_mac(); 563 + if (!priv->mac) 564 + priv->mac = of_get_mac_address(pdev->dev.of_node); 565 566 priv->clk_ppe = clk_get(&pdev->dev, NULL); 567 if (IS_ERR(priv->clk_ppe)) 568 -- 569 1.7.10.4 570 -
trunk/target/linux/lantiq/patches-3.8/0038-owrt-lantiq-handle-vmmc-memory-reservation.patch
r36013 r36014 1 From 6af001cc662f4aa3740c550ac43c6b6f75df67c8 Mon Sep 17 00:00:00 2001 2 From: John Crispin <blogic@openwrt.org> 3 Date: Wed, 13 Mar 2013 10:04:01 +0100 4 Subject: [PATCH 38/40] owrt: lantiq: handle vmmc memory reservation 5 6 --- 7 arch/mips/lantiq/xway/Makefile | 2 +- 8 arch/mips/lantiq/xway/vmmc.c | 63 ++++++++++++++++++++++++++++++++++++++++ 9 2 files changed, 64 insertions(+), 1 deletion(-) 10 create mode 100644 arch/mips/lantiq/xway/vmmc.c 11 12 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile 13 index 51f0eba..3a01d22 100644 1 14 --- a/arch/mips/lantiq/xway/Makefile 2 15 +++ b/arch/mips/lantiq/xway/Makefile 3 16 @@ -1,6 +1,6 @@ 4 obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o17 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o 5 18 6 19 -obj-y += eth_mac.o … … 9 22 10 23 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o 24 diff --git a/arch/mips/lantiq/xway/vmmc.c b/arch/mips/lantiq/xway/vmmc.c 25 new file mode 100644 26 index 0000000..6dedf77 11 27 --- /dev/null 12 28 +++ b/arch/mips/lantiq/xway/vmmc.c … … 36 52 +EXPORT_SYMBOL(ltq_get_cp1_base); 37 53 + 38 +static int __devinitvmmc_probe(struct platform_device *pdev)54 +static int vmmc_probe(struct platform_device *pdev) 39 55 +{ 40 56 +#define CP1_SIZE (1 << 20) … … 75 91 + 76 92 +module_platform_driver(vmmc_driver); 93 -- 94 1.7.10.4 95 -
trunk/target/linux/lantiq/patches-3.8/0039-owrt-lantiq-backport-old-timer-code.patch
r36013 r36014 1 --- /dev/null 2 +++ b/arch/mips/lantiq/xway/timer.c 3 @@ -0,0 +1,845 @@ 4 +#ifndef CONFIG_SOC_AMAZON_SE 5 + 6 +#include <linux/kernel.h> 7 +#include <linux/module.h> 8 +#include <linux/version.h> 9 +#include <linux/types.h> 10 +#include <linux/fs.h> 11 +#include <linux/miscdevice.h> 12 +#include <linux/init.h> 13 +#include <linux/uaccess.h> 14 +#include <linux/unistd.h> 15 +#include <linux/errno.h> 16 +#include <linux/interrupt.h> 17 +#include <linux/sched.h> 18 + 19 +#include <asm/irq.h> 20 +#include <asm/div64.h> 21 +#include "../clk.h" 22 + 23 +#include <lantiq_soc.h> 24 +#include <lantiq_irq.h> 25 +#include <lantiq_timer.h> 26 + 27 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 28 + 29 +#ifdef TIMER1A 30 +#define FIRST_TIMER TIMER1A 31 +#else 32 +#define FIRST_TIMER 2 33 +#endif 34 + 35 +/* 36 + * GPTC divider is set or not. 37 + */ 38 +#define GPTU_CLC_RMC_IS_SET 0 39 + 40 +/* 41 + * Timer Interrupt (IRQ) 42 + */ 43 +/* Must be adjusted when ICU driver is available */ 44 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) 45 + 46 +/* 47 + * Bits Operation 48 + */ 49 +#define GET_BITS(x, msb, lsb) \ 50 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) 51 +#define SET_BITS(x, msb, lsb, value) \ 52 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ 53 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) 54 + 55 +/* 56 + * GPTU Register Mapping 57 + */ 58 +#define LQ_GPTU (KSEG1 + 0x1E100A00) 59 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) 60 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) 61 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 62 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 63 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 64 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 65 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) 66 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) 67 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) 68 + 69 +/* 70 + * Clock Control Register 71 + */ 72 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) 73 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) 74 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) 75 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) 76 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) 77 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) 78 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) 79 + 80 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) 81 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) 82 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) 83 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) 84 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) 85 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) 86 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) 87 + 88 +/* 89 + * ID Register 90 + */ 91 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) 92 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) 93 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) 94 + 95 +/* 96 + * Control Register of Timer/Counter nX 97 + * n is the index of block (1 based index) 98 + * X is either A or B 99 + */ 100 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) 101 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) 102 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) 103 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) 104 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) 105 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ 106 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) 107 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) 108 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) 109 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) 110 + 111 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) 112 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) 113 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) 114 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) 115 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) 116 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) 117 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) 118 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) 119 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) 120 + 121 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) 122 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) 123 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) 124 + 125 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) 126 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) 127 + 128 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) 129 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) 130 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) 131 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) 132 +#define TIMER_FLAG_NONE_EDGE 0x0000 133 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) 134 +#define TIMER_FLAG_REAL 0x0000 135 +#define TIMER_FLAG_INVERT 0x0040 136 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) 137 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) 138 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) 139 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 140 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) 141 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) 142 + 143 +struct timer_dev_timer { 144 + unsigned int f_irq_on; 145 + unsigned int irq; 146 + unsigned int flag; 147 + unsigned long arg1; 148 + unsigned long arg2; 149 +}; 150 + 151 +struct timer_dev { 152 + struct mutex gptu_mutex; 153 + unsigned int number_of_timers; 154 + unsigned int occupation; 155 + unsigned int f_gptu_on; 156 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; 157 +}; 158 + 159 + 160 +unsigned int ltq_get_fpi_bus_clock(int fpi) { 161 + struct clk *clk = clk_get_fpi(); 162 + return clk_get_rate(clk); 163 +} 164 + 165 + 166 +static long gptu_ioctl(struct file *, unsigned int, unsigned long); 167 +static int gptu_open(struct inode *, struct file *); 168 +static int gptu_release(struct inode *, struct file *); 169 + 170 +static struct file_operations gptu_fops = { 171 + .owner = THIS_MODULE, 172 + .unlocked_ioctl = gptu_ioctl, 173 + .open = gptu_open, 174 + .release = gptu_release 175 +}; 176 + 177 +static struct miscdevice gptu_miscdev = { 178 + .minor = MISC_DYNAMIC_MINOR, 179 + .name = "gptu", 180 + .fops = &gptu_fops, 181 +}; 182 + 183 +static struct timer_dev timer_dev; 184 + 185 +static irqreturn_t timer_irq_handler(int irq, void *p) 186 +{ 187 + unsigned int timer; 188 + unsigned int flag; 189 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; 190 + 191 + timer = irq - TIMER_INTERRUPT; 192 + if (timer < timer_dev.number_of_timers 193 + && dev_timer == &timer_dev.timer[timer]) { 194 + /* Clear interrupt. */ 195 + ltq_w32(1 << timer, LQ_GPTU_IRNCR); 196 + 197 + /* Call user hanler or signal. */ 198 + flag = dev_timer->flag; 199 + if (!(timer & 0x01) 200 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { 201 + /* 16-bit timer or timer A of 32-bit timer */ 202 + switch (TIMER_FLAG_MASK_HANDLE(flag)) { 203 + case TIMER_FLAG_CALLBACK_IN_IRQ: 204 + case TIMER_FLAG_CALLBACK_IN_HB: 205 + if (dev_timer->arg1) 206 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); 207 + break; 208 + case TIMER_FLAG_SIGNAL: 209 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); 210 + break; 211 + } 212 + } 213 + } 214 + return IRQ_HANDLED; 215 +} 216 + 217 +static inline void lq_enable_gptu(void) 218 +{ 219 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); 220 + clk_enable(clk); 221 + 222 + //ltq_pmu_enable(PMU_GPT); 223 + 224 + /* Set divider as 1, disable write protection for SPEN, enable module. */ 225 + *LQ_GPTU_CLC = 226 + GPTU_CLC_SMC_SET(0x00) | 227 + GPTU_CLC_RMC_SET(0x01) | 228 + GPTU_CLC_FSOE_SET(0) | 229 + GPTU_CLC_SBWE_SET(1) | 230 + GPTU_CLC_EDIS_SET(0) | 231 + GPTU_CLC_SPEN_SET(0) | 232 + GPTU_CLC_DISR_SET(0); 233 +} 234 + 235 +static inline void lq_disable_gptu(void) 236 +{ 237 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); 238 + ltq_w32(0x00, LQ_GPTU_IRNEN); 239 + ltq_w32(0xfff, LQ_GPTU_IRNCR); 240 + 241 + /* Set divider as 0, enable write protection for SPEN, disable module. */ 242 + *LQ_GPTU_CLC = 243 + GPTU_CLC_SMC_SET(0x00) | 244 + GPTU_CLC_RMC_SET(0x00) | 245 + GPTU_CLC_FSOE_SET(0) | 246 + GPTU_CLC_SBWE_SET(0) | 247 + GPTU_CLC_EDIS_SET(0) | 248 + GPTU_CLC_SPEN_SET(0) | 249 + GPTU_CLC_DISR_SET(1); 250 + 251 + clk_enable(clk); 252 +} 253 + 254 +int lq_request_timer(unsigned int timer, unsigned int flag, 255 + unsigned long value, unsigned long arg1, unsigned long arg2) 256 +{ 257 + int ret = 0; 258 + unsigned int con_reg, irnen_reg; 259 + int n, X; 260 + 261 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers) 262 + return -EINVAL; 263 + 264 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", 265 + timer, flag, value); 266 + 267 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) 268 + value &= 0xFFFF; 269 + else 270 + timer &= ~0x01; 271 + 272 + mutex_lock(&timer_dev.gptu_mutex); 273 + 274 + /* 275 + * Allocate timer. 276 + */ 277 + if (timer < FIRST_TIMER) { 278 + unsigned int mask; 279 + unsigned int shift; 280 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ 281 + unsigned int offset = TIMER2A; 282 + 283 + /* 284 + * Pick up a free timer. 285 + */ 286 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { 287 + mask = 1 << offset; 288 + shift = 1; 289 + } else { 290 + mask = 3 << offset; 291 + shift = 2; 292 + } 293 + for (timer = offset; 294 + timer < offset + timer_dev.number_of_timers; 295 + timer += shift, mask <<= shift) 296 + if (!(timer_dev.occupation & mask)) { 297 + timer_dev.occupation |= mask; 298 + break; 299 + } 300 + if (timer >= offset + timer_dev.number_of_timers) { 301 + printk("failed![%d]\n", __LINE__); 302 + mutex_unlock(&timer_dev.gptu_mutex); 303 + return -EINVAL; 304 + } else 305 + ret = timer; 306 + } else { 307 + register unsigned int mask; 308 + 309 + /* 310 + * Check if the requested timer is free. 311 + */ 312 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 313 + if ((timer_dev.occupation & mask)) { 314 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", 315 + __LINE__, mask, timer_dev.occupation); 316 + mutex_unlock(&timer_dev.gptu_mutex); 317 + return -EBUSY; 318 + } else { 319 + timer_dev.occupation |= mask; 320 + ret = 0; 321 + } 322 + } 323 + 324 + /* 325 + * Prepare control register value. 326 + */ 327 + switch (TIMER_FLAG_MASK_EDGE(flag)) { 328 + default: 329 + case TIMER_FLAG_NONE_EDGE: 330 + con_reg = GPTU_CON_EDGE_SET(0x00); 331 + break; 332 + case TIMER_FLAG_RISE_EDGE: 333 + con_reg = GPTU_CON_EDGE_SET(0x01); 334 + break; 335 + case TIMER_FLAG_FALL_EDGE: 336 + con_reg = GPTU_CON_EDGE_SET(0x02); 337 + break; 338 + case TIMER_FLAG_ANY_EDGE: 339 + con_reg = GPTU_CON_EDGE_SET(0x03); 340 + break; 341 + } 342 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) 343 + con_reg |= 344 + TIMER_FLAG_MASK_SRC(flag) == 345 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : 346 + GPTU_CON_SRC_EXT_SET(0); 347 + else 348 + con_reg |= 349 + TIMER_FLAG_MASK_SRC(flag) == 350 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : 351 + GPTU_CON_SRC_EG_SET(0); 352 + con_reg |= 353 + TIMER_FLAG_MASK_SYNC(flag) == 354 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : 355 + GPTU_CON_SYNC_SET(1); 356 + con_reg |= 357 + TIMER_FLAG_MASK_INVERT(flag) == 358 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); 359 + con_reg |= 360 + TIMER_FLAG_MASK_SIZE(flag) == 361 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : 362 + GPTU_CON_EXT_SET(1); 363 + con_reg |= 364 + TIMER_FLAG_MASK_STOP(flag) == 365 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); 366 + con_reg |= 367 + TIMER_FLAG_MASK_TYPE(flag) == 368 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : 369 + GPTU_CON_CNT_SET(1); 370 + con_reg |= 371 + TIMER_FLAG_MASK_DIR(flag) == 372 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); 373 + 374 + /* 375 + * Fill up running data. 376 + */ 377 + timer_dev.timer[timer - FIRST_TIMER].flag = flag; 378 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; 379 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; 380 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 381 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; 382 + 383 + /* 384 + * Enable GPTU module. 385 + */ 386 + if (!timer_dev.f_gptu_on) { 387 + lq_enable_gptu(); 388 + timer_dev.f_gptu_on = 1; 389 + } 390 + 391 + /* 392 + * Enable IRQ. 393 + */ 394 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { 395 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) 396 + timer_dev.timer[timer - FIRST_TIMER].arg1 = 397 + (unsigned long) find_task_by_vpid((int) arg1); 398 + 399 + irnen_reg = 1 << (timer - FIRST_TIMER); 400 + 401 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL 402 + || (TIMER_FLAG_MASK_HANDLE(flag) == 403 + TIMER_FLAG_CALLBACK_IN_IRQ 404 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) { 405 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); 406 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; 407 + } 408 + } else 409 + irnen_reg = 0; 410 + 411 + /* 412 + * Write config register, reload value and enable interrupt. 413 + */ 414 + n = timer >> 1; 415 + X = timer & 0x01; 416 + *LQ_GPTU_CON(n, X) = con_reg; 417 + *LQ_GPTU_RELOAD(n, X) = value; 418 + /* printk("reload value = %d\n", (u32)value); */ 419 + *LQ_GPTU_IRNEN |= irnen_reg; 420 + 421 + mutex_unlock(&timer_dev.gptu_mutex); 422 + printk("successful!\n"); 423 + return ret; 424 +} 425 +EXPORT_SYMBOL(lq_request_timer); 426 + 427 +int lq_free_timer(unsigned int timer) 428 +{ 429 + unsigned int flag; 430 + unsigned int mask; 431 + int n, X; 432 + 433 + if (!timer_dev.f_gptu_on) 434 + return -EINVAL; 435 + 436 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 437 + return -EINVAL; 438 + 439 + mutex_lock(&timer_dev.gptu_mutex); 440 + 441 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 442 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 443 + timer &= ~0x01; 444 + 445 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 446 + if (((timer_dev.occupation & mask) ^ mask)) { 447 + mutex_unlock(&timer_dev.gptu_mutex); 448 + return -EINVAL; 449 + } 450 + 451 + n = timer >> 1; 452 + X = timer & 0x01; 453 + 454 + if (GPTU_CON_EN(n, X)) 455 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); 456 + 457 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); 458 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); 459 + 460 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { 461 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); 462 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; 463 + } 464 + 465 + timer_dev.occupation &= ~mask; 466 + if (!timer_dev.occupation && timer_dev.f_gptu_on) { 467 + lq_disable_gptu(); 468 + timer_dev.f_gptu_on = 0; 469 + } 470 + 471 + mutex_unlock(&timer_dev.gptu_mutex); 472 + 473 + return 0; 474 +} 475 +EXPORT_SYMBOL(lq_free_timer); 476 + 477 +int lq_start_timer(unsigned int timer, int is_resume) 478 +{ 479 + unsigned int flag; 480 + unsigned int mask; 481 + int n, X; 482 + 483 + if (!timer_dev.f_gptu_on) 484 + return -EINVAL; 485 + 486 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 487 + return -EINVAL; 488 + 489 + mutex_lock(&timer_dev.gptu_mutex); 490 + 491 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 492 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 493 + timer &= ~0x01; 494 + 495 + mask = (TIMER_FLAG_MASK_SIZE(flag) == 496 + TIMER_FLAG_16BIT ? 1 : 3) << timer; 497 + if (((timer_dev.occupation & mask) ^ mask)) { 498 + mutex_unlock(&timer_dev.gptu_mutex); 499 + return -EINVAL; 500 + } 501 + 502 + n = timer >> 1; 503 + X = timer & 0x01; 504 + 505 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); 506 + 507 + 508 + mutex_unlock(&timer_dev.gptu_mutex); 509 + 510 + return 0; 511 +} 512 +EXPORT_SYMBOL(lq_start_timer); 513 + 514 +int lq_stop_timer(unsigned int timer) 515 +{ 516 + unsigned int flag; 517 + unsigned int mask; 518 + int n, X; 519 + 520 + if (!timer_dev.f_gptu_on) 521 + return -EINVAL; 522 + 523 + if (timer < FIRST_TIMER 524 + || timer >= FIRST_TIMER + timer_dev.number_of_timers) 525 + return -EINVAL; 526 + 527 + mutex_lock(&timer_dev.gptu_mutex); 528 + 529 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 530 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 531 + timer &= ~0x01; 532 + 533 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 534 + if (((timer_dev.occupation & mask) ^ mask)) { 535 + mutex_unlock(&timer_dev.gptu_mutex); 536 + return -EINVAL; 537 + } 538 + 539 + n = timer >> 1; 540 + X = timer & 0x01; 541 + 542 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); 543 + 544 + mutex_unlock(&timer_dev.gptu_mutex); 545 + 546 + return 0; 547 +} 548 +EXPORT_SYMBOL(lq_stop_timer); 549 + 550 +int lq_reset_counter_flags(u32 timer, u32 flags) 551 +{ 552 + unsigned int oflag; 553 + unsigned int mask, con_reg; 554 + int n, X; 555 + 556 + if (!timer_dev.f_gptu_on) 557 + return -EINVAL; 558 + 559 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 560 + return -EINVAL; 561 + 562 + mutex_lock(&timer_dev.gptu_mutex); 563 + 564 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag; 565 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) 566 + timer &= ~0x01; 567 + 568 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 569 + if (((timer_dev.occupation & mask) ^ mask)) { 570 + mutex_unlock(&timer_dev.gptu_mutex); 571 + return -EINVAL; 572 + } 573 + 574 + switch (TIMER_FLAG_MASK_EDGE(flags)) { 575 + default: 576 + case TIMER_FLAG_NONE_EDGE: 577 + con_reg = GPTU_CON_EDGE_SET(0x00); 578 + break; 579 + case TIMER_FLAG_RISE_EDGE: 580 + con_reg = GPTU_CON_EDGE_SET(0x01); 581 + break; 582 + case TIMER_FLAG_FALL_EDGE: 583 + con_reg = GPTU_CON_EDGE_SET(0x02); 584 + break; 585 + case TIMER_FLAG_ANY_EDGE: 586 + con_reg = GPTU_CON_EDGE_SET(0x03); 587 + break; 588 + } 589 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) 590 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); 591 + else 592 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); 593 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); 594 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); 595 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); 596 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); 597 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); 598 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); 599 + 600 + timer_dev.timer[timer - FIRST_TIMER].flag = flags; 601 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) 602 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; 603 + 604 + n = timer >> 1; 605 + X = timer & 0x01; 606 + 607 + *LQ_GPTU_CON(n, X) = con_reg; 608 + smp_wmb(); 609 + mutex_unlock(&timer_dev.gptu_mutex); 610 + return 0; 611 +} 612 +EXPORT_SYMBOL(lq_reset_counter_flags); 613 + 614 +int lq_get_count_value(unsigned int timer, unsigned long *value) 615 +{ 616 + unsigned int flag; 617 + unsigned int mask; 618 + int n, X; 619 + 620 + if (!timer_dev.f_gptu_on) 621 + return -EINVAL; 622 + 623 + if (timer < FIRST_TIMER 624 + || timer >= FIRST_TIMER + timer_dev.number_of_timers) 625 + return -EINVAL; 626 + 627 + mutex_lock(&timer_dev.gptu_mutex); 628 + 629 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 630 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 631 + timer &= ~0x01; 632 + 633 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 634 + if (((timer_dev.occupation & mask) ^ mask)) { 635 + mutex_unlock(&timer_dev.gptu_mutex); 636 + return -EINVAL; 637 + } 638 + 639 + n = timer >> 1; 640 + X = timer & 0x01; 641 + 642 + *value = *LQ_GPTU_COUNT(n, X); 643 + 644 + 645 + mutex_unlock(&timer_dev.gptu_mutex); 646 + 647 + return 0; 648 +} 649 +EXPORT_SYMBOL(lq_get_count_value); 650 + 651 +u32 lq_cal_divider(unsigned long freq) 652 +{ 653 + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); 654 + u32 clock_divider = 1; 655 + module_freq = fpi * 1000; 656 + do_div(module_freq, clock_divider * freq); 657 + return module_freq; 658 +} 659 +EXPORT_SYMBOL(lq_cal_divider); 660 + 661 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, 662 + int is_ext_src, unsigned int handle_flag, unsigned long arg1, 663 + unsigned long arg2) 664 +{ 665 + unsigned long divider; 666 + unsigned int flag; 667 + 668 + divider = lq_cal_divider(freq); 669 + if (divider == 0) 670 + return -EINVAL; 671 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) 672 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) 673 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) 674 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN 675 + | TIMER_FLAG_MASK_HANDLE(handle_flag); 676 + 677 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", 678 + timer, freq, divider); 679 + return lq_request_timer(timer, flag, divider, arg1, arg2); 680 +} 681 +EXPORT_SYMBOL(lq_set_timer); 682 + 683 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, 684 + unsigned long arg1, unsigned long arg2) 685 +{ 686 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); 687 + return lq_request_timer(timer, flag, reload, arg1, arg2); 688 +} 689 +EXPORT_SYMBOL(lq_set_counter); 690 + 691 +static long gptu_ioctl(struct file *file, unsigned int cmd, 692 + unsigned long arg) 693 +{ 694 + int ret; 695 + struct gptu_ioctl_param param; 696 + 697 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) 698 + return -EFAULT; 699 + copy_from_user(¶m, (void *) arg, sizeof(param)); 700 + 701 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER 702 + || GPTU_SET_COUNTER) && param.timer < 2) 703 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) 704 + && !access_ok(VERIFY_WRITE, arg, 705 + sizeof(struct gptu_ioctl_param))) 706 + return -EFAULT; 707 + 708 + switch (cmd) { 709 + case GPTU_REQUEST_TIMER: 710 + ret = lq_request_timer(param.timer, param.flag, param.value, 711 + (unsigned long) param.pid, 712 + (unsigned long) param.sig); 713 + if (ret > 0) { 714 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 715 + timer, &ret, sizeof(&ret)); 716 + ret = 0; 717 + } 718 + break; 719 + case GPTU_FREE_TIMER: 720 + ret = lq_free_timer(param.timer); 721 + break; 722 + case GPTU_START_TIMER: 723 + ret = lq_start_timer(param.timer, param.flag); 724 + break; 725 + case GPTU_STOP_TIMER: 726 + ret = lq_stop_timer(param.timer); 727 + break; 728 + case GPTU_GET_COUNT_VALUE: 729 + ret = lq_get_count_value(param.timer, ¶m.value); 730 + if (!ret) 731 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 732 + value, ¶m.value, 733 + sizeof(param.value)); 734 + break; 735 + case GPTU_CALCULATE_DIVIDER: 736 + param.value = lq_cal_divider(param.value); 737 + if (param.value == 0) 738 + ret = -EINVAL; 739 + else { 740 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 741 + value, ¶m.value, 742 + sizeof(param.value)); 743 + ret = 0; 744 + } 745 + break; 746 + case GPTU_SET_TIMER: 747 + ret = lq_set_timer(param.timer, param.value, 748 + TIMER_FLAG_MASK_STOP(param.flag) != 749 + TIMER_FLAG_ONCE ? 1 : 0, 750 + TIMER_FLAG_MASK_SRC(param.flag) == 751 + TIMER_FLAG_EXT_SRC ? 1 : 0, 752 + TIMER_FLAG_MASK_HANDLE(param.flag) == 753 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : 754 + TIMER_FLAG_NO_HANDLE, 755 + (unsigned long) param.pid, 756 + (unsigned long) param.sig); 757 + if (ret > 0) { 758 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 759 + timer, &ret, sizeof(&ret)); 760 + ret = 0; 761 + } 762 + break; 763 + case GPTU_SET_COUNTER: 764 + lq_set_counter(param.timer, param.flag, param.value, 0, 0); 765 + if (ret > 0) { 766 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 767 + timer, &ret, sizeof(&ret)); 768 + ret = 0; 769 + } 770 + break; 771 + default: 772 + ret = -ENOTTY; 773 + } 774 + 775 + return ret; 776 +} 777 + 778 +static int gptu_open(struct inode *inode, struct file *file) 779 +{ 780 + return 0; 781 +} 782 + 783 +static int gptu_release(struct inode *inode, struct file *file) 784 +{ 785 + return 0; 786 +} 787 + 788 +int __init lq_gptu_init(void) 789 +{ 790 + int ret; 791 + unsigned int i; 792 + 793 + ltq_w32(0, LQ_GPTU_IRNEN); 794 + ltq_w32(0xfff, LQ_GPTU_IRNCR); 795 + 796 + memset(&timer_dev, 0, sizeof(timer_dev)); 797 + mutex_init(&timer_dev.gptu_mutex); 798 + 799 + lq_enable_gptu(); 800 + timer_dev.number_of_timers = GPTU_ID_CFG * 2; 801 + lq_disable_gptu(); 802 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) 803 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; 804 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); 805 + 806 + ret = misc_register(&gptu_miscdev); 807 + if (ret) { 808 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); 809 + return ret; 810 + } else { 811 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); 812 + } 813 + 814 + for (i = 0; i < timer_dev.number_of_timers; i++) { 815 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); 816 + if (ret) { 817 + for (; i >= 0; i--) 818 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); 819 + misc_deregister(&gptu_miscdev); 820 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); 821 + return ret; 822 + } else { 823 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i; 824 + disable_irq(timer_dev.timer[i].irq); 825 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); 826 + } 827 + } 828 + 829 + return 0; 830 +} 831 + 832 +void __exit lq_gptu_exit(void) 833 +{ 834 + unsigned int i; 835 + 836 + for (i = 0; i < timer_dev.number_of_timers; i++) { 837 + if (timer_dev.timer[i].f_irq_on) 838 + disable_irq(timer_dev.timer[i].irq); 839 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); 840 + } 841 + lq_disable_gptu(); 842 + misc_deregister(&gptu_miscdev); 843 +} 844 + 845 +module_init(lq_gptu_init); 846 +module_exit(lq_gptu_exit); 847 + 848 +#endif 1 From 225313fe4112a487954e7f7e3be995854b7c9ffa Mon Sep 17 00:00:00 2001 2 From: John Crispin <blogic@openwrt.org> 3 Date: Wed, 13 Mar 2013 10:01:49 +0100 4 Subject: [PATCH 39/40] owrt: lantiq: backport old timer code 5 6 --- 7 arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ 8 arch/mips/lantiq/xway/Makefile | 2 +- 9 arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ 10 3 files changed, 1001 insertions(+), 1 deletion(-) 11 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h 12 create mode 100644 arch/mips/lantiq/xway/timer.c 13 14 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h 15 new file mode 100644 16 index 0000000..ef564ab 849 17 --- /dev/null 850 18 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h … … 1005 173 + 1006 174 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ 175 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile 176 index 3a01d22..ea8706f 100644 1007 177 --- a/arch/mips/lantiq/xway/Makefile 1008 178 +++ b/arch/mips/lantiq/xway/Makefile 1009 @@ -1, 3 +1,3@@179 @@ -1,4 +1,4 @@ 1010 180 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o 1011 181 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o 1012 182 1013 obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o 183 obj-y += eth_mac.o vmmc.o 184 obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o 185 diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c 186 new file mode 100644 187 index 0000000..1c0fdb8 188 --- /dev/null 189 +++ b/arch/mips/lantiq/xway/timer.c 190 @@ -0,0 +1,845 @@ 191 +#ifndef CONFIG_SOC_AMAZON_SE 192 + 193 +#include <linux/kernel.h> 194 +#include <linux/module.h> 195 +#include <linux/version.h> 196 +#include <linux/types.h> 197 +#include <linux/fs.h> 198 +#include <linux/miscdevice.h> 199 +#include <linux/init.h> 200 +#include <linux/uaccess.h> 201 +#include <linux/unistd.h> 202 +#include <linux/errno.h> 203 +#include <linux/interrupt.h> 204 +#include <linux/sched.h> 205 + 206 +#include <asm/irq.h> 207 +#include <asm/div64.h> 208 +#include "../clk.h" 209 + 210 +#include <lantiq_soc.h> 211 +#include <lantiq_irq.h> 212 +#include <lantiq_timer.h> 213 + 214 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 215 + 216 +#ifdef TIMER1A 217 +#define FIRST_TIMER TIMER1A 218 +#else 219 +#define FIRST_TIMER 2 220 +#endif 221 + 222 +/* 223 + * GPTC divider is set or not. 224 + */ 225 +#define GPTU_CLC_RMC_IS_SET 0 226 + 227 +/* 228 + * Timer Interrupt (IRQ) 229 + */ 230 +/* Must be adjusted when ICU driver is available */ 231 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) 232 + 233 +/* 234 + * Bits Operation 235 + */ 236 +#define GET_BITS(x, msb, lsb) \ 237 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) 238 +#define SET_BITS(x, msb, lsb, value) \ 239 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ 240 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) 241 + 242 +/* 243 + * GPTU Register Mapping 244 + */ 245 +#define LQ_GPTU (KSEG1 + 0x1E100A00) 246 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) 247 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) 248 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 249 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 250 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 251 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ 252 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) 253 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) 254 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) 255 + 256 +/* 257 + * Clock Control Register 258 + */ 259 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) 260 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) 261 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) 262 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) 263 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) 264 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) 265 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) 266 + 267 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) 268 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) 269 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) 270 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) 271 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) 272 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) 273 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) 274 + 275 +/* 276 + * ID Register 277 + */ 278 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) 279 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) 280 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) 281 + 282 +/* 283 + * Control Register of Timer/Counter nX 284 + * n is the index of block (1 based index) 285 + * X is either A or B 286 + */ 287 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) 288 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) 289 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) 290 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) 291 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) 292 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ 293 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) 294 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) 295 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) 296 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) 297 + 298 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) 299 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) 300 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) 301 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) 302 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) 303 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) 304 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) 305 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) 306 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) 307 + 308 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) 309 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) 310 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) 311 + 312 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) 313 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) 314 + 315 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) 316 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) 317 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) 318 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) 319 +#define TIMER_FLAG_NONE_EDGE 0x0000 320 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) 321 +#define TIMER_FLAG_REAL 0x0000 322 +#define TIMER_FLAG_INVERT 0x0040 323 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) 324 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) 325 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) 326 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 327 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) 328 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) 329 + 330 +struct timer_dev_timer { 331 + unsigned int f_irq_on; 332 + unsigned int irq; 333 + unsigned int flag; 334 + unsigned long arg1; 335 + unsigned long arg2; 336 +}; 337 + 338 +struct timer_dev { 339 + struct mutex gptu_mutex; 340 + unsigned int number_of_timers; 341 + unsigned int occupation; 342 + unsigned int f_gptu_on; 343 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; 344 +}; 345 + 346 + 347 +unsigned int ltq_get_fpi_bus_clock(int fpi) { 348 + struct clk *clk = clk_get_fpi(); 349 + return clk_get_rate(clk); 350 +} 351 + 352 + 353 +static long gptu_ioctl(struct file *, unsigned int, unsigned long); 354 +static int gptu_open(struct inode *, struct file *); 355 +static int gptu_release(struct inode *, struct file *); 356 + 357 +static struct file_operations gptu_fops = { 358 + .owner = THIS_MODULE, 359 + .unlocked_ioctl = gptu_ioctl, 360 + .open = gptu_open, 361 + .release = gptu_release 362 +}; 363 + 364 +static struct miscdevice gptu_miscdev = { 365 + .minor = MISC_DYNAMIC_MINOR, 366 + .name = "gptu", 367 + .fops = &gptu_fops, 368 +}; 369 + 370 +static struct timer_dev timer_dev; 371 + 372 +static irqreturn_t timer_irq_handler(int irq, void *p) 373 +{ 374 + unsigned int timer; 375 + unsigned int flag; 376 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; 377 + 378 + timer = irq - TIMER_INTERRUPT; 379 + if (timer < timer_dev.number_of_timers 380 + && dev_timer == &timer_dev.timer[timer]) { 381 + /* Clear interrupt. */ 382 + ltq_w32(1 << timer, LQ_GPTU_IRNCR); 383 + 384 + /* Call user hanler or signal. */ 385 + flag = dev_timer->flag; 386 + if (!(timer & 0x01) 387 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { 388 + /* 16-bit timer or timer A of 32-bit timer */ 389 + switch (TIMER_FLAG_MASK_HANDLE(flag)) { 390 + case TIMER_FLAG_CALLBACK_IN_IRQ: 391 + case TIMER_FLAG_CALLBACK_IN_HB: 392 + if (dev_timer->arg1) 393 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); 394 + break; 395 + case TIMER_FLAG_SIGNAL: 396 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); 397 + break; 398 + } 399 + } 400 + } 401 + return IRQ_HANDLED; 402 +} 403 + 404 +static inline void lq_enable_gptu(void) 405 +{ 406 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); 407 + clk_enable(clk); 408 + 409 + //ltq_pmu_enable(PMU_GPT); 410 + 411 + /* Set divider as 1, disable write protection for SPEN, enable module. */ 412 + *LQ_GPTU_CLC = 413 + GPTU_CLC_SMC_SET(0x00) | 414 + GPTU_CLC_RMC_SET(0x01) | 415 + GPTU_CLC_FSOE_SET(0) | 416 + GPTU_CLC_SBWE_SET(1) | 417 + GPTU_CLC_EDIS_SET(0) | 418 + GPTU_CLC_SPEN_SET(0) | 419 + GPTU_CLC_DISR_SET(0); 420 +} 421 + 422 +static inline void lq_disable_gptu(void) 423 +{ 424 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); 425 + ltq_w32(0x00, LQ_GPTU_IRNEN); 426 + ltq_w32(0xfff, LQ_GPTU_IRNCR); 427 + 428 + /* Set divider as 0, enable write protection for SPEN, disable module. */ 429 + *LQ_GPTU_CLC = 430 + GPTU_CLC_SMC_SET(0x00) | 431 + GPTU_CLC_RMC_SET(0x00) | 432 + GPTU_CLC_FSOE_SET(0) | 433 + GPTU_CLC_SBWE_SET(0) | 434 + GPTU_CLC_EDIS_SET(0) | 435 + GPTU_CLC_SPEN_SET(0) | 436 + GPTU_CLC_DISR_SET(1); 437 + 438 + clk_enable(clk); 439 +} 440 + 441 +int lq_request_timer(unsigned int timer, unsigned int flag, 442 + unsigned long value, unsigned long arg1, unsigned long arg2) 443 +{ 444 + int ret = 0; 445 + unsigned int con_reg, irnen_reg; 446 + int n, X; 447 + 448 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers) 449 + return -EINVAL; 450 + 451 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", 452 + timer, flag, value); 453 + 454 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) 455 + value &= 0xFFFF; 456 + else 457 + timer &= ~0x01; 458 + 459 + mutex_lock(&timer_dev.gptu_mutex); 460 + 461 + /* 462 + * Allocate timer. 463 + */ 464 + if (timer < FIRST_TIMER) { 465 + unsigned int mask; 466 + unsigned int shift; 467 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ 468 + unsigned int offset = TIMER2A; 469 + 470 + /* 471 + * Pick up a free timer. 472 + */ 473 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { 474 + mask = 1 << offset; 475 + shift = 1; 476 + } else { 477 + mask = 3 << offset; 478 + shift = 2; 479 + } 480 + for (timer = offset; 481 + timer < offset + timer_dev.number_of_timers; 482 + timer += shift, mask <<= shift) 483 + if (!(timer_dev.occupation & mask)) { 484 + timer_dev.occupation |= mask; 485 + break; 486 + } 487 + if (timer >= offset + timer_dev.number_of_timers) { 488 + printk("failed![%d]\n", __LINE__); 489 + mutex_unlock(&timer_dev.gptu_mutex); 490 + return -EINVAL; 491 + } else 492 + ret = timer; 493 + } else { 494 + register unsigned int mask; 495 + 496 + /* 497 + * Check if the requested timer is free. 498 + */ 499 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 500 + if ((timer_dev.occupation & mask)) { 501 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", 502 + __LINE__, mask, timer_dev.occupation); 503 + mutex_unlock(&timer_dev.gptu_mutex); 504 + return -EBUSY; 505 + } else { 506 + timer_dev.occupation |= mask; 507 + ret = 0; 508 + } 509 + } 510 + 511 + /* 512 + * Prepare control register value. 513 + */ 514 + switch (TIMER_FLAG_MASK_EDGE(flag)) { 515 + default: 516 + case TIMER_FLAG_NONE_EDGE: 517 + con_reg = GPTU_CON_EDGE_SET(0x00); 518 + break; 519 + case TIMER_FLAG_RISE_EDGE: 520 + con_reg = GPTU_CON_EDGE_SET(0x01); 521 + break; 522 + case TIMER_FLAG_FALL_EDGE: 523 + con_reg = GPTU_CON_EDGE_SET(0x02); 524 + break; 525 + case TIMER_FLAG_ANY_EDGE: 526 + con_reg = GPTU_CON_EDGE_SET(0x03); 527 + break; 528 + } 529 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) 530 + con_reg |= 531 + TIMER_FLAG_MASK_SRC(flag) == 532 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : 533 + GPTU_CON_SRC_EXT_SET(0); 534 + else 535 + con_reg |= 536 + TIMER_FLAG_MASK_SRC(flag) == 537 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : 538 + GPTU_CON_SRC_EG_SET(0); 539 + con_reg |= 540 + TIMER_FLAG_MASK_SYNC(flag) == 541 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : 542 + GPTU_CON_SYNC_SET(1); 543 + con_reg |= 544 + TIMER_FLAG_MASK_INVERT(flag) == 545 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); 546 + con_reg |= 547 + TIMER_FLAG_MASK_SIZE(flag) == 548 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : 549 + GPTU_CON_EXT_SET(1); 550 + con_reg |= 551 + TIMER_FLAG_MASK_STOP(flag) == 552 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); 553 + con_reg |= 554 + TIMER_FLAG_MASK_TYPE(flag) == 555 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : 556 + GPTU_CON_CNT_SET(1); 557 + con_reg |= 558 + TIMER_FLAG_MASK_DIR(flag) == 559 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); 560 + 561 + /* 562 + * Fill up running data. 563 + */ 564 + timer_dev.timer[timer - FIRST_TIMER].flag = flag; 565 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; 566 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; 567 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 568 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; 569 + 570 + /* 571 + * Enable GPTU module. 572 + */ 573 + if (!timer_dev.f_gptu_on) { 574 + lq_enable_gptu(); 575 + timer_dev.f_gptu_on = 1; 576 + } 577 + 578 + /* 579 + * Enable IRQ. 580 + */ 581 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { 582 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) 583 + timer_dev.timer[timer - FIRST_TIMER].arg1 = 584 + (unsigned long) find_task_by_vpid((int) arg1); 585 + 586 + irnen_reg = 1 << (timer - FIRST_TIMER); 587 + 588 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL 589 + || (TIMER_FLAG_MASK_HANDLE(flag) == 590 + TIMER_FLAG_CALLBACK_IN_IRQ 591 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) { 592 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); 593 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; 594 + } 595 + } else 596 + irnen_reg = 0; 597 + 598 + /* 599 + * Write config register, reload value and enable interrupt. 600 + */ 601 + n = timer >> 1; 602 + X = timer & 0x01; 603 + *LQ_GPTU_CON(n, X) = con_reg; 604 + *LQ_GPTU_RELOAD(n, X) = value; 605 + /* printk("reload value = %d\n", (u32)value); */ 606 + *LQ_GPTU_IRNEN |= irnen_reg; 607 + 608 + mutex_unlock(&timer_dev.gptu_mutex); 609 + printk("successful!\n"); 610 + return ret; 611 +} 612 +EXPORT_SYMBOL(lq_request_timer); 613 + 614 +int lq_free_timer(unsigned int timer) 615 +{ 616 + unsigned int flag; 617 + unsigned int mask; 618 + int n, X; 619 + 620 + if (!timer_dev.f_gptu_on) 621 + return -EINVAL; 622 + 623 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 624 + return -EINVAL; 625 + 626 + mutex_lock(&timer_dev.gptu_mutex); 627 + 628 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 629 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 630 + timer &= ~0x01; 631 + 632 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 633 + if (((timer_dev.occupation & mask) ^ mask)) { 634 + mutex_unlock(&timer_dev.gptu_mutex); 635 + return -EINVAL; 636 + } 637 + 638 + n = timer >> 1; 639 + X = timer & 0x01; 640 + 641 + if (GPTU_CON_EN(n, X)) 642 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); 643 + 644 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); 645 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); 646 + 647 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { 648 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); 649 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; 650 + } 651 + 652 + timer_dev.occupation &= ~mask; 653 + if (!timer_dev.occupation && timer_dev.f_gptu_on) { 654 + lq_disable_gptu(); 655 + timer_dev.f_gptu_on = 0; 656 + } 657 + 658 + mutex_unlock(&timer_dev.gptu_mutex); 659 + 660 + return 0; 661 +} 662 +EXPORT_SYMBOL(lq_free_timer); 663 + 664 +int lq_start_timer(unsigned int timer, int is_resume) 665 +{ 666 + unsigned int flag; 667 + unsigned int mask; 668 + int n, X; 669 + 670 + if (!timer_dev.f_gptu_on) 671 + return -EINVAL; 672 + 673 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 674 + return -EINVAL; 675 + 676 + mutex_lock(&timer_dev.gptu_mutex); 677 + 678 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 679 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 680 + timer &= ~0x01; 681 + 682 + mask = (TIMER_FLAG_MASK_SIZE(flag) == 683 + TIMER_FLAG_16BIT ? 1 : 3) << timer; 684 + if (((timer_dev.occupation & mask) ^ mask)) { 685 + mutex_unlock(&timer_dev.gptu_mutex); 686 + return -EINVAL; 687 + } 688 + 689 + n = timer >> 1; 690 + X = timer & 0x01; 691 + 692 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); 693 + 694 + 695 + mutex_unlock(&timer_dev.gptu_mutex); 696 + 697 + return 0; 698 +} 699 +EXPORT_SYMBOL(lq_start_timer); 700 + 701 +int lq_stop_timer(unsigned int timer) 702 +{ 703 + unsigned int flag; 704 + unsigned int mask; 705 + int n, X; 706 + 707 + if (!timer_dev.f_gptu_on) 708 + return -EINVAL; 709 + 710 + if (timer < FIRST_TIMER 711 + || timer >= FIRST_TIMER + timer_dev.number_of_timers) 712 + return -EINVAL; 713 + 714 + mutex_lock(&timer_dev.gptu_mutex); 715 + 716 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 717 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 718 + timer &= ~0x01; 719 + 720 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 721 + if (((timer_dev.occupation & mask) ^ mask)) { 722 + mutex_unlock(&timer_dev.gptu_mutex); 723 + return -EINVAL; 724 + } 725 + 726 + n = timer >> 1; 727 + X = timer & 0x01; 728 + 729 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); 730 + 731 + mutex_unlock(&timer_dev.gptu_mutex); 732 + 733 + return 0; 734 +} 735 +EXPORT_SYMBOL(lq_stop_timer); 736 + 737 +int lq_reset_counter_flags(u32 timer, u32 flags) 738 +{ 739 + unsigned int oflag; 740 + unsigned int mask, con_reg; 741 + int n, X; 742 + 743 + if (!timer_dev.f_gptu_on) 744 + return -EINVAL; 745 + 746 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) 747 + return -EINVAL; 748 + 749 + mutex_lock(&timer_dev.gptu_mutex); 750 + 751 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag; 752 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) 753 + timer &= ~0x01; 754 + 755 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 756 + if (((timer_dev.occupation & mask) ^ mask)) { 757 + mutex_unlock(&timer_dev.gptu_mutex); 758 + return -EINVAL; 759 + } 760 + 761 + switch (TIMER_FLAG_MASK_EDGE(flags)) { 762 + default: 763 + case TIMER_FLAG_NONE_EDGE: 764 + con_reg = GPTU_CON_EDGE_SET(0x00); 765 + break; 766 + case TIMER_FLAG_RISE_EDGE: 767 + con_reg = GPTU_CON_EDGE_SET(0x01); 768 + break; 769 + case TIMER_FLAG_FALL_EDGE: 770 + con_reg = GPTU_CON_EDGE_SET(0x02); 771 + break; 772 + case TIMER_FLAG_ANY_EDGE: 773 + con_reg = GPTU_CON_EDGE_SET(0x03); 774 + break; 775 + } 776 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) 777 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); 778 + else 779 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); 780 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); 781 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); 782 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); 783 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); 784 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); 785 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); 786 + 787 + timer_dev.timer[timer - FIRST_TIMER].flag = flags; 788 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) 789 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; 790 + 791 + n = timer >> 1; 792 + X = timer & 0x01; 793 + 794 + *LQ_GPTU_CON(n, X) = con_reg; 795 + smp_wmb(); 796 + mutex_unlock(&timer_dev.gptu_mutex); 797 + return 0; 798 +} 799 +EXPORT_SYMBOL(lq_reset_counter_flags); 800 + 801 +int lq_get_count_value(unsigned int timer, unsigned long *value) 802 +{ 803 + unsigned int flag; 804 + unsigned int mask; 805 + int n, X; 806 + 807 + if (!timer_dev.f_gptu_on) 808 + return -EINVAL; 809 + 810 + if (timer < FIRST_TIMER 811 + || timer >= FIRST_TIMER + timer_dev.number_of_timers) 812 + return -EINVAL; 813 + 814 + mutex_lock(&timer_dev.gptu_mutex); 815 + 816 + flag = timer_dev.timer[timer - FIRST_TIMER].flag; 817 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) 818 + timer &= ~0x01; 819 + 820 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; 821 + if (((timer_dev.occupation & mask) ^ mask)) { 822 + mutex_unlock(&timer_dev.gptu_mutex); 823 + return -EINVAL; 824 + } 825 + 826 + n = timer >> 1; 827 + X = timer & 0x01; 828 + 829 + *value = *LQ_GPTU_COUNT(n, X); 830 + 831 + 832 + mutex_unlock(&timer_dev.gptu_mutex); 833 + 834 + return 0; 835 +} 836 +EXPORT_SYMBOL(lq_get_count_value); 837 + 838 +u32 lq_cal_divider(unsigned long freq) 839 +{ 840 + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); 841 + u32 clock_divider = 1; 842 + module_freq = fpi * 1000; 843 + do_div(module_freq, clock_divider * freq); 844 + return module_freq; 845 +} 846 +EXPORT_SYMBOL(lq_cal_divider); 847 + 848 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, 849 + int is_ext_src, unsigned int handle_flag, unsigned long arg1, 850 + unsigned long arg2) 851 +{ 852 + unsigned long divider; 853 + unsigned int flag; 854 + 855 + divider = lq_cal_divider(freq); 856 + if (divider == 0) 857 + return -EINVAL; 858 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) 859 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) 860 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) 861 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN 862 + | TIMER_FLAG_MASK_HANDLE(handle_flag); 863 + 864 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", 865 + timer, freq, divider); 866 + return lq_request_timer(timer, flag, divider, arg1, arg2); 867 +} 868 +EXPORT_SYMBOL(lq_set_timer); 869 + 870 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, 871 + unsigned long arg1, unsigned long arg2) 872 +{ 873 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); 874 + return lq_request_timer(timer, flag, reload, arg1, arg2); 875 +} 876 +EXPORT_SYMBOL(lq_set_counter); 877 + 878 +static long gptu_ioctl(struct file *file, unsigned int cmd, 879 + unsigned long arg) 880 +{ 881 + int ret; 882 + struct gptu_ioctl_param param; 883 + 884 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) 885 + return -EFAULT; 886 + copy_from_user(¶m, (void *) arg, sizeof(param)); 887 + 888 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER 889 + || GPTU_SET_COUNTER) && param.timer < 2) 890 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) 891 + && !access_ok(VERIFY_WRITE, arg, 892 + sizeof(struct gptu_ioctl_param))) 893 + return -EFAULT; 894 + 895 + switch (cmd) { 896 + case GPTU_REQUEST_TIMER: 897 + ret = lq_request_timer(param.timer, param.flag, param.value, 898 + (unsigned long) param.pid, 899 + (unsigned long) param.sig); 900 + if (ret > 0) { 901 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 902 + timer, &ret, sizeof(&ret)); 903 + ret = 0; 904 + } 905 + break; 906 + case GPTU_FREE_TIMER: 907 + ret = lq_free_timer(param.timer); 908 + break; 909 + case GPTU_START_TIMER: 910 + ret = lq_start_timer(param.timer, param.flag); 911 + break; 912 + case GPTU_STOP_TIMER: 913 + ret = lq_stop_timer(param.timer); 914 + break; 915 + case GPTU_GET_COUNT_VALUE: 916 + ret = lq_get_count_value(param.timer, ¶m.value); 917 + if (!ret) 918 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 919 + value, ¶m.value, 920 + sizeof(param.value)); 921 + break; 922 + case GPTU_CALCULATE_DIVIDER: 923 + param.value = lq_cal_divider(param.value); 924 + if (param.value == 0) 925 + ret = -EINVAL; 926 + else { 927 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 928 + value, ¶m.value, 929 + sizeof(param.value)); 930 + ret = 0; 931 + } 932 + break; 933 + case GPTU_SET_TIMER: 934 + ret = lq_set_timer(param.timer, param.value, 935 + TIMER_FLAG_MASK_STOP(param.flag) != 936 + TIMER_FLAG_ONCE ? 1 : 0, 937 + TIMER_FLAG_MASK_SRC(param.flag) == 938 + TIMER_FLAG_EXT_SRC ? 1 : 0, 939 + TIMER_FLAG_MASK_HANDLE(param.flag) == 940 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : 941 + TIMER_FLAG_NO_HANDLE, 942 + (unsigned long) param.pid, 943 + (unsigned long) param.sig); 944 + if (ret > 0) { 945 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 946 + timer, &ret, sizeof(&ret)); 947 + ret = 0; 948 + } 949 + break; 950 + case GPTU_SET_COUNTER: 951 + lq_set_counter(param.timer, param.flag, param.value, 0, 0); 952 + if (ret > 0) { 953 + copy_to_user(&((struct gptu_ioctl_param *) arg)-> 954 + timer, &ret, sizeof(&ret)); 955 + ret = 0; 956 + } 957 + break; 958 + default: 959 + ret = -ENOTTY; 960 + } 961 + 962 + return ret; 963 +} 964 + 965 +static int gptu_open(struct inode *inode, struct file *file) 966 +{ 967 + return 0; 968 +} 969 + 970 +static int gptu_release(struct inode *inode, struct file *file) 971 +{ 972 + return 0; 973 +} 974 + 975 +int __init lq_gptu_init(void) 976 +{ 977 + int ret; 978 + unsigned int i; 979 + 980 + ltq_w32(0, LQ_GPTU_IRNEN); 981 + ltq_w32(0xfff, LQ_GPTU_IRNCR); 982 + 983 + memset(&timer_dev, 0, sizeof(timer_dev)); 984 + mutex_init(&timer_dev.gptu_mutex); 985 + 986 + lq_enable_gptu(); 987 + timer_dev.number_of_timers = GPTU_ID_CFG * 2; 988 + lq_disable_gptu(); 989 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) 990 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; 991 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); 992 + 993 + ret = misc_register(&gptu_miscdev); 994 + if (ret) { 995 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); 996 + return ret; 997 + } else { 998 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); 999 + } 1000 + 1001 + for (i = 0; i < timer_dev.number_of_timers; i++) { 1002 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); 1003 + if (ret) { 1004 + for (; i >= 0; i--) 1005 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); 1006 + misc_deregister(&gptu_miscdev); 1007 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); 1008 + return ret; 1009 + } else { 1010 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i; 1011 + disable_irq(timer_dev.timer[i].irq); 1012 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); 1013 + } 1014 + } 1015 + 1016 + return 0; 1017 +} 1018 + 1019 +void __exit lq_gptu_exit(void) 1020 +{ 1021 + unsigned int i; 1022 + 1023 + for (i = 0; i < timer_dev.number_of_timers; i++) { 1024 + if (timer_dev.timer[i].f_irq_on) 1025 + disable_irq(timer_dev.timer[i].irq); 1026 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); 1027 + } 1028 + lq_disable_gptu(); 1029 + misc_deregister(&gptu_miscdev); 1030 +} 1031 + 1032 +module_init(lq_gptu_init); 1033 +module_exit(lq_gptu_exit); 1034 + 1035 +#endif 1036 -- 1037 1.7.10.4 1038 -
trunk/target/linux/lantiq/patches-3.8/0040-owrt-lantiq-add-atm-hack.patch
r36013 r36014 1 From 8d2a7d1fb561c9cb098c2b13ded34fe0f49dcca5Mon Sep 17 00:00:00 20011 From ae15f50544e6012c998ef59f6c12e334da3c9bff Mon Sep 17 00:00:00 2001 2 2 From: John Crispin <blogic@openwrt.org> 3 3 Date: Fri, 3 Aug 2012 10:27:25 +0200 4 Subject: [PATCH 20/25] owrt atm4 Subject: [PATCH 40/40] owrt: lantiq: add atm hack 5 5 6 6 --- 7 arch/mips/lantiq/irq.c | 2 ++ 8 arch/mips/mm/cache.c | 2 ++ 9 net/atm/common.c | 6 ++++++ 10 net/atm/proc.c | 2 +- 11 4 files changed, 11 insertions(+), 1 deletions(-) 7 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ 8 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ 9 arch/mips/lantiq/irq.c | 2 + 10 arch/mips/mm/cache.c | 2 + 11 include/uapi/linux/atm.h | 6 + 12 net/atm/common.c | 6 + 13 net/atm/proc.c | 2 +- 14 7 files changed, 416 insertions(+), 1 deletion(-) 15 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h 16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h 12 17 13 --- a/arch/mips/lantiq/irq.c 14 +++ b/arch/mips/lantiq/irq.c 15 @@ -14,6 +14,7 @@ 16 #include <linux/of_platform.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 +#include <linux/module.h> 20 21 #include <asm/bootinfo.h> 22 #include <asm/irq_cpu.h> 23 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_dat 24 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); 25 ltq_icu_w32(im, BIT(offset), isr); 26 } 27 +EXPORT_SYMBOL(ltq_mask_and_ack_irq); 28 29 static void ltq_ack_irq(struct irq_data *d) 30 { 31 --- a/arch/mips/mm/cache.c 32 +++ b/arch/mips/mm/cache.c 33 @@ -58,6 +58,8 @@ void (*_dma_cache_wback)(unsigned long s 34 void (*_dma_cache_inv)(unsigned long start, unsigned long size); 35 36 EXPORT_SYMBOL(_dma_cache_wback_inv); 37 +EXPORT_SYMBOL(_dma_cache_wback); 38 +EXPORT_SYMBOL(_dma_cache_inv); 39 40 #endif /* CONFIG_DMA_NONCOHERENT */ 41 42 --- a/net/atm/common.c 43 +++ b/net/atm/common.c 44 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc 45 write_unlock_irq(&vcc_sklist_lock); 46 } 47 48 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; 49 +EXPORT_SYMBOL(ifx_atm_alloc_tx); 50 + 51 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) 52 { 53 struct sk_buff *skb; 54 struct sock *sk = sk_atm(vcc); 55 56 + if (ifx_atm_alloc_tx != NULL) 57 + return ifx_atm_alloc_tx(vcc, size); 58 + 59 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { 60 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", 61 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); 62 --- a/net/atm/proc.c 63 +++ b/net/atm/proc.c 64 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil 65 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) 66 { 67 static const char *const class_name[] = { 68 - "off", "UBR", "CBR", "VBR", "ABR"}; 69 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; 70 static const char *const aal_name[] = { 71 "---", "1", "2", "3/4", /* 0- 3 */ 72 "???", "5", "???", "???", /* 4- 7 */ 18 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h 19 new file mode 100644 20 index 0000000..bf045a9 73 21 --- /dev/null 74 22 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h … … 270 218 +#endif // IFX_ATM_H 271 219 + 220 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h 221 new file mode 100644 222 index 0000000..698e5c3 272 223 --- /dev/null 273 224 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h … … 476 427 +#endif // IFX_PTM_H 477 428 + 429 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c 430 index 5119487..6d2c486 100644 431 --- a/arch/mips/lantiq/irq.c 432 +++ b/arch/mips/lantiq/irq.c 433 @@ -14,6 +14,7 @@ 434 #include <linux/of_platform.h> 435 #include <linux/of_address.h> 436 #include <linux/of_irq.h> 437 +#include <linux/module.h> 438 439 #include <asm/bootinfo.h> 440 #include <asm/irq_cpu.h> 441 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d) 442 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); 443 ltq_icu_w32(im, BIT(offset), isr); 444 } 445 +EXPORT_SYMBOL(ltq_mask_and_ack_irq); 446 447 static void ltq_ack_irq(struct irq_data *d) 448 { 449 diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c 450 index 07cec44..a3e3872 100644 451 --- a/arch/mips/mm/cache.c 452 +++ b/arch/mips/mm/cache.c 453 @@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size); 454 void (*_dma_cache_inv)(unsigned long start, unsigned long size); 455 456 EXPORT_SYMBOL(_dma_cache_wback_inv); 457 +EXPORT_SYMBOL(_dma_cache_wback); 458 +EXPORT_SYMBOL(_dma_cache_inv); 459 460 #endif /* CONFIG_DMA_NONCOHERENT */ 461 462 diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h 463 index 88399db..78c8bbc 100644 478 464 --- a/include/uapi/linux/atm.h 479 465 +++ b/include/uapi/linux/atm.h … … 493 479 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ 494 480 int max_pcr; /* maximum PCR in cells per second */ 481 diff --git a/net/atm/common.c b/net/atm/common.c 482 index 806fc0a..82bc78e 100644 483 --- a/net/atm/common.c 484 +++ b/net/atm/common.c 485 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk) 486 write_unlock_irq(&vcc_sklist_lock); 487 } 488 489 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; 490 +EXPORT_SYMBOL(ifx_atm_alloc_tx); 491 + 492 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) 493 { 494 struct sk_buff *skb; 495 struct sock *sk = sk_atm(vcc); 496 497 + if (ifx_atm_alloc_tx != NULL) 498 + return ifx_atm_alloc_tx(vcc, size); 499 + 500 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { 501 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", 502 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); 503 diff --git a/net/atm/proc.c b/net/atm/proc.c 504 index 0d020de..9fdb539 100644 505 --- a/net/atm/proc.c 506 +++ b/net/atm/proc.c 507 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos) 508 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) 509 { 510 static const char *const class_name[] = { 511 - "off", "UBR", "CBR", "VBR", "ABR"}; 512 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; 513 static const char *const aal_name[] = { 514 "---", "1", "2", "3/4", /* 0- 3 */ 515 "???", "5", "???", "???", /* 4- 7 */ 516 -- 517 1.7.10.4 518
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