Changeset 33362


Ignore:
Timestamp:
2012-09-10T16:38:01+02:00 (5 years ago)
Author:
juhosg
Message:

ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch

    r33335 r33362  
    3939+ 
    4040+       cpu_pll = nint * ath79_ref_clk.rate / ref_div; 
    41 +       cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); 
     41+       cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); 
    4242+       cpu_pll /= (1 << out_div); 
    4343+ 
     
    5353+ 
    5454+       ddr_pll = nint * ath79_ref_clk.rate / ref_div; 
    55 +       ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); 
     55+       ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); 
    5656+       ddr_pll /= (1 << out_div); 
    5757+ 
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