Changeset 32812


Ignore:
Timestamp:
2012-07-24T22:37:50+02:00 (6 years ago)
Author:
blogic
Message:

[ramips] uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@…>

File:
1 edited

Legend:

Unmodified
Added
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  • trunk/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c

    r31401 r32812  
    6161                } 
    6262                rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; 
    63                 rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10; 
     63                rt305x_uart_clk.rate = 40000000; 
    6464                rt305x_wdt_clk.rate = rt305x_sys_clk.rate; 
    6565        } else { 
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