Changeset 29013


Ignore:
Timestamp:
2011-11-13T12:26:59+01:00 (6 years ago)
Author:
juhosg
Message:

ar71xx: set MII interface speed from the set_speed callbacks

Location:
trunk/target/linux/ar71xx/files
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

    r29012 r29013  
    207207} 
    208208 
     209static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed) 
     210{ 
     211        void __iomem *base; 
     212        unsigned int mii_speed; 
     213        u32 t; 
     214 
     215        switch (speed) { 
     216        case SPEED_10: 
     217                mii_speed =  MII_CTRL_SPEED_10; 
     218                break; 
     219        case SPEED_100: 
     220                mii_speed =  MII_CTRL_SPEED_100; 
     221                break; 
     222        case SPEED_1000: 
     223                mii_speed =  MII_CTRL_SPEED_1000; 
     224                break; 
     225        default: 
     226                BUG(); 
     227        } 
     228 
     229        base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); 
     230 
     231        t = __raw_readl(base + reg); 
     232        t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); 
     233        t |= mii_speed  << MII_CTRL_SPEED_SHIFT; 
     234        __raw_writel(t, base + reg); 
     235 
     236        iounmap(base); 
     237} 
     238 
    209239void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask) 
    210240{ 
     
    322352        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, 
    323353                        val, AR71XX_ETH0_PLL_SHIFT); 
     354        ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed); 
    324355} 
    325356 
     
    330361        ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, 
    331362                         val, AR71XX_ETH1_PLL_SHIFT); 
     363        ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed); 
    332364} 
    333365 
     
    358390        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, 
    359391                         val, AR91XX_ETH0_PLL_SHIFT); 
     392        ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed); 
    360393} 
    361394 
     
    366399        ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, 
    367400                         val, AR91XX_ETH1_PLL_SHIFT); 
     401        ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed); 
    368402} 
    369403 
  • trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

    r29010 r29013  
    818818 
    819819#define MII_CTRL_IF_MASK        3 
     820#define MII_CTRL_SPEED_SHIFT    4 
     821#define MII_CTRL_SPEED_MASK     3 
     822#define MII_CTRL_SPEED_10       0 
     823#define MII_CTRL_SPEED_100      1 
     824#define MII_CTRL_SPEED_1000     2 
    820825 
    821826#define MII0_CTRL_IF_GMII       0 
  • trunk/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

    r29012 r29013  
    534534        u32 ifctl; 
    535535        u32 fifo5; 
    536         u32 mii_speed; 
    537536 
    538537        if (!ag->link) { 
     
    559558        switch (ag->speed) { 
    560559        case SPEED_1000: 
    561                 mii_speed =  MII_CTRL_SPEED_1000; 
    562560                cfg2 |= MAC_CFG2_IF_1000; 
    563561                fifo5 |= FIFO_CFG5_BM; 
    564562                break; 
    565563        case SPEED_100: 
    566                 mii_speed = MII_CTRL_SPEED_100; 
    567564                cfg2 |= MAC_CFG2_IF_10_100; 
    568565                ifctl |= MAC_IFCTL_SPEED; 
    569566                break; 
    570567        case SPEED_10: 
    571                 mii_speed = MII_CTRL_SPEED_10; 
    572568                cfg2 |= MAC_CFG2_IF_10_100; 
    573569                break; 
     
    586582        if (pdata->set_speed) 
    587583                pdata->set_speed(ag->speed); 
    588  
    589         ag71xx_mii_ctrl_set_speed(ag, mii_speed); 
    590584 
    591585        ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 
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