Changeset 28973


Ignore:
Timestamp:
2011-11-12T11:54:08+01:00 (6 years ago)
Author:
juhosg
Message:

ar71xx: fix AR934X clock frequency calculation

Location:
trunk/target/linux/ar71xx/files/arch/mips
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

    r27079 r28973  
    184184{ 
    185185        u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 
     186        u32 cpu_pll, ddr_pll; 
    186187 
    187188        if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) 
     
    189190        else 
    190191                ar71xx_ref_freq = 25 * 1000 * 1000; 
    191  
    192         clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); 
    193192 
    194193        pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); 
     
    197196        nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll); 
    198197        frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); 
    199         postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); 
    200         ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / 
    201                           (postdiv + 1); 
    202  
     198 
     199        cpu_pll = nint * ar71xx_ref_freq / ref_div; 
     200        cpu_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 6)); 
     201        cpu_pll /= (1 << out_div); 
     202 
     203        pll = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CONFIG); 
    203204        out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); 
    204205        ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); 
    205206        nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll); 
    206207        frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); 
    207         postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); 
    208         ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / 
    209                           (postdiv + 1); 
    210  
    211         postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); 
    212  
    213         if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { 
    214                 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1); 
     208 
     209        ddr_pll = nint * ar71xx_ref_freq / ref_div; 
     210        ddr_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 10)); 
     211        ddr_pll /= (1 << out_div); 
     212 
     213        clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); 
     214 
     215        if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) { 
     216                ar71xx_cpu_freq = ar71xx_ref_freq; 
    215217        } else { 
    216                 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); 
    217         } 
    218  
     218                postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); 
     219 
     220                if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 
     221                        ar71xx_cpu_freq = cpu_pll / (postdiv + 1); 
     222                else 
     223                        ar71xx_cpu_freq = ddr_pll / (postdiv + 1); 
     224        } 
     225 
     226        if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) { 
     227                ar71xx_ddr_freq = ar71xx_ref_freq; 
     228        } else { 
     229                postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); 
     230 
     231                if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 
     232                        ar71xx_ddr_freq = ddr_pll / (postdiv + 1); 
     233                else 
     234                        ar71xx_ddr_freq = cpu_pll / (postdiv + 1); 
     235        } 
     236 
     237        if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) { 
     238                ar71xx_ahb_freq = ar71xx_ref_freq; 
     239        } else { 
     240                postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); 
     241 
     242                if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 
     243                        ar71xx_ahb_freq = ddr_pll / (postdiv + 1); 
     244                else 
     245                        ar71xx_ahb_freq = cpu_pll / (postdiv + 1); 
     246        } 
    219247} 
    220248 
  • trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

    r28705 r28973  
    213213 
    214214#define AR934X_PLL_REG_CPU_CONFIG       0x00 
     215#define AR934X_PLL_REG_DDR_CONFIG       0x04 
    215216#define AR934X_PLL_REG_DDR_CTRL_CLOCK   0x8 
    216217 
     
    372373 
    373374#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET        1 
     375 
     376#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS          BIT(2) 
     377#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS          BIT(3) 
     378#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS          BIT(4) 
     379#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL      BIT(20) 
     380#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL      BIT(21) 
     381#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL      BIT(24) 
    374382 
    375383extern void __iomem *ar71xx_pll_base; 
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