Changeset 27246
- Timestamp:
- 2011-06-21T12:05:51+02:00 (7 years ago)
- Location:
- trunk/target/linux/brcm63xx
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
r27236 r27246 27 27 --- /dev/null 28 28 +++ b/arch/mips/bcm63xx/dev-spi.c 29 @@ -0,0 +1, 131@@29 @@ -0,0 +1,98 @@ 30 30 +/* 31 31 + * This file is subject to the terms and conditions of the GNU General Public … … 33 33 + * for more details. 34 34 + * 35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>35 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org> 36 36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 37 37 + */ … … 50 50 + */ 51 51 +static const unsigned long bcm96338_regs_spi[] = { 52 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD, 53 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS, 54 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST, 55 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK, 56 + [SPI_ST] = SPI_BCM_6338_SPI_ST, 57 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG, 58 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE, 59 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL, 60 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL, 61 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL, 62 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA, 63 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA, 52 + __GEN_SPI_REGS_TABLE(6338) 64 53 +}; 65 54 + 66 55 +static const unsigned long bcm96348_regs_spi[] = { 67 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD, 68 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS, 69 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST, 70 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK, 71 + [SPI_ST] = SPI_BCM_6348_SPI_ST, 72 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG, 73 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE, 74 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL, 75 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL, 76 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL, 77 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA, 78 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA, 56 + __GEN_SPI_REGS_TABLE(6348) 79 57 +}; 80 58 + 81 59 +static const unsigned long bcm96358_regs_spi[] = { 82 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD, 83 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS, 84 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST, 85 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK, 86 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS, 87 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG, 88 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE, 89 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL, 90 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL, 91 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL, 92 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA, 93 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA, 60 + __GEN_SPI_REGS_TABLE(6358) 94 61 +}; 95 62 + … … 215 182 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */ 216 183 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02 217 +#define SPI_BCM_6338_SPI_ MASK_INT_ST 0x03184 +#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03 218 185 +#define SPI_BCM_6338_SPI_INT_MASK 0x04 219 186 +#define SPI_BCM_6338_SPI_ST 0x05 … … 229 196 + 230 197 +/* BCM 6348 SPI core */ 231 +#define SPI_BCM_6348_SPI_ MASK_INT_ST 0x00198 +#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00 232 199 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01 233 200 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */ … … 245 212 + 246 213 +/* BCM 6358 SPI core */ 247 +#define SPI_BCM_6358_ MSG_CTL0x00 /* 16-bits register */214 +#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */ 248 215 + 249 216 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02 … … 256 223 + 257 224 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702 258 +#define SPI_BCM_6358_SPI_ MASK_INT_ST 0x703225 +#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703 259 226 + 260 227 +#define SPI_BCM_6358_SPI_INT_MASK 0x704 261 228 + 262 +#define SPI_BCM_6358_SPI_ST ATUS0x705229 +#define SPI_BCM_6358_SPI_ST 0x705 263 230 + 264 231 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706 … … 847 814 --- /dev/null 848 815 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h 849 @@ -0,0 +1, 126@@816 @@ -0,0 +1,85 @@ 850 817 +#ifndef BCM63XX_DEV_SPI_H 851 818 +#define BCM63XX_DEV_SPI_H … … 879 846 +}; 880 847 + 848 +#define __GEN_SPI_RSET_BASE(__cpu, __rset) \ 849 + case SPI_## __rset: \ 850 + return SPI_BCM_## __cpu ##_SPI_## __rset ##; 851 + 852 +#define __GEN_SPI_RSET(__cpu) \ 853 + switch (reg) { \ 854 + __GEN_SPI_RSET_BASE(__cpu, CMD) \ 855 + __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \ 856 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \ 857 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \ 858 + __GEN_SPI_RSET_BASE(__cpu, ST) \ 859 + __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \ 860 + __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \ 861 + __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \ 862 + __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \ 863 + __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \ 864 + __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \ 865 + __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \ 866 + } 867 + 868 +#define __GEN_SPI_REGS_TABLE(__cpu) \ 869 + [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \ 870 + [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \ 871 + [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \ 872 + [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \ 873 + [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \ 874 + [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \ 875 + [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \ 876 + [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \ 877 + [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \ 878 + [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \ 879 + [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \ 880 + [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA, 881 + 881 882 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) 882 883 +{ … … 886 887 +#else 887 888 +#ifdef CONFIG_BCM63XX_CPU_6338 888 +switch (reg) { 889 + case SPI_CMD: 890 + return SPI_BCM_6338_SPI_CMD; 891 + case SPI_INT_STATUS: 892 + return SPI_BCM_6338_SPI_INT_STATUS; 893 + case SPI_INT_MASK_ST: 894 + return SPI_BCM_6338_SPI_MASK_INT_ST; 895 + case SPI_INT_MASK: 896 + return SPI_BCM_6338_SPI_INT_MASK; 897 + case SPI_ST: 898 + return SPI_BCM_6338_SPI_ST; 899 + case SPI_CLK_CFG: 900 + return SPI_BCM_6338_SPI_CLK_CFG; 901 + case SPI_FILL_BYTE: 902 + return SPI_BCM_6338_SPI_FILL_BYTE; 903 + case SPI_MSG_TAIL: 904 + return SPI_BCM_6338_SPI_MSG_TAIL; 905 + case SPI_RX_TAIL: 906 + return SPI_BCM_6338_SPI_RX_TAIL; 907 + case SPI_MSG_CTL: 908 + return SPI_BCM_6338_SPI_MSG_CTL; 909 + case SPI_MSG_DATA: 910 + return SPI_BCM_6338_SPI_MSG_DATA; 911 + case SPI_RX_DATA: 912 + return SPI_BCM_6338_SPI_RX_DATA; 913 +} 889 + __GEN_SPI_RSET(6338) 914 890 +#endif 915 891 +#ifdef CONFIG_BCM63XX_CPU_6348 916 +switch (reg) { 917 + case SPI_CMD: 918 + return SPI_BCM_6348_SPI_CMD; 919 + case SPI_INT_MASK_ST: 920 + return SPI_BCM_6348_SPI_MASK_INT_ST; 921 + case SPI_INT_MASK: 922 + return SPI_BCM_6348_SPI_INT_MASK; 923 + case SPI_INT_STATUS: 924 + return SPI_BCM_6348_SPI_INT_STATUS; 925 + case SPI_ST: 926 + return SPI_BCM_6348_SPI_ST; 927 + case SPI_CLK_CFG: 928 + return SPI_BCM_6348_SPI_CLK_CFG; 929 + case SPI_FILL_BYTE: 930 + return SPI_BCM_6348_SPI_FILL_BYTE; 931 + case SPI_MSG_TAIL: 932 + return SPI_BCM_6348_SPI_MSG_TAIL; 933 + case SPI_RX_TAIL: 934 + return SPI_BCM_6348_SPI_RX_TAIL; 935 + case SPI_MSG_CTL: 936 + return SPI_BCM_6348_SPI_MSG_CTL; 937 + case SPI_MSG_DATA: 938 + return SPI_BCM_6348_SPI_MSG_DATA; 939 + case SPI_RX_DATA: 940 + return SPI_BCM_6348_SPI_RX_DATA; 941 +} 892 + __GEN_SPI_RSET(6348) 942 893 +#endif 943 894 +#ifdef CONFIG_BCM63XX_CPU_6358 944 +switch (reg) { 945 + case SPI_CMD: 946 + return SPI_BCM_6358_SPI_CMD; 947 + case SPI_INT_STATUS: 948 + return SPI_BCM_6358_SPI_INT_STATUS; 949 + case SPI_INT_MASK_ST: 950 + return SPI_BCM_6358_SPI_MASK_INT_ST; 951 + case SPI_INT_MASK: 952 + return SPI_BCM_6358_SPI_INT_MASK; 953 + case SPI_ST: 954 + return SPI_BCM_6358_SPI_STATUS; 955 + case SPI_CLK_CFG: 956 + return SPI_BCM_6358_SPI_CLK_CFG; 957 + case SPI_FILL_BYTE: 958 + return SPI_BCM_6358_SPI_FILL_BYTE; 959 + case SPI_MSG_TAIL: 960 + return SPI_BCM_6358_SPI_MSG_TAIL; 961 + case SPI_RX_TAIL: 962 + return SPI_BCM_6358_SPI_RX_TAIL; 963 + case SPI_MSG_CTL: 964 + return SPI_BCM_6358_MSG_CTL; 965 + case SPI_MSG_DATA: 966 + return SPI_BCM_6358_SPI_MSG_DATA; 967 + case SPI_RX_DATA: 968 + return SPI_BCM_6358_SPI_RX_DATA; 969 +} 895 + __GEN_SPI_RSET(6358) 970 896 +#endif 971 897 +#endif -
trunk/target/linux/brcm63xx/patches-3.0/240-spi.patch
r27236 r27246 27 27 --- /dev/null 28 28 +++ b/arch/mips/bcm63xx/dev-spi.c 29 @@ -0,0 +1, 131@@29 @@ -0,0 +1,98 @@ 30 30 +/* 31 31 + * This file is subject to the terms and conditions of the GNU General Public … … 33 33 + * for more details. 34 34 + * 35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>35 + * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org> 36 36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 37 37 + */ … … 50 50 + */ 51 51 +static const unsigned long bcm96338_regs_spi[] = { 52 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD, 53 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS, 54 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST, 55 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK, 56 + [SPI_ST] = SPI_BCM_6338_SPI_ST, 57 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG, 58 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE, 59 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL, 60 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL, 61 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL, 62 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA, 63 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA, 52 + __GEN_SPI_REGS_TABLE(6338) 64 53 +}; 65 54 + 66 55 +static const unsigned long bcm96348_regs_spi[] = { 67 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD, 68 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS, 69 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST, 70 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK, 71 + [SPI_ST] = SPI_BCM_6348_SPI_ST, 72 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG, 73 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE, 74 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL, 75 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL, 76 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL, 77 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA, 78 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA, 56 + __GEN_SPI_REGS_TABLE(6348) 79 57 +}; 80 58 + 81 59 +static const unsigned long bcm96358_regs_spi[] = { 82 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD, 83 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS, 84 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST, 85 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK, 86 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS, 87 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG, 88 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE, 89 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL, 90 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL, 91 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL, 92 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA, 93 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA, 60 + __GEN_SPI_REGS_TABLE(6358) 94 61 +}; 95 62 + … … 215 182 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */ 216 183 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02 217 +#define SPI_BCM_6338_SPI_ MASK_INT_ST 0x03184 +#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03 218 185 +#define SPI_BCM_6338_SPI_INT_MASK 0x04 219 186 +#define SPI_BCM_6338_SPI_ST 0x05 … … 229 196 + 230 197 +/* BCM 6348 SPI core */ 231 +#define SPI_BCM_6348_SPI_ MASK_INT_ST 0x00198 +#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00 232 199 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01 233 200 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */ … … 245 212 + 246 213 +/* BCM 6358 SPI core */ 247 +#define SPI_BCM_6358_ MSG_CTL0x00 /* 16-bits register */214 +#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */ 248 215 + 249 216 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02 … … 256 223 + 257 224 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702 258 +#define SPI_BCM_6358_SPI_ MASK_INT_ST 0x703225 +#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703 259 226 + 260 227 +#define SPI_BCM_6358_SPI_INT_MASK 0x704 261 228 + 262 +#define SPI_BCM_6358_SPI_ST ATUS0x705229 +#define SPI_BCM_6358_SPI_ST 0x705 263 230 + 264 231 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706 … … 847 814 --- /dev/null 848 815 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h 849 @@ -0,0 +1, 126@@816 @@ -0,0 +1,85 @@ 850 817 +#ifndef BCM63XX_DEV_SPI_H 851 818 +#define BCM63XX_DEV_SPI_H … … 879 846 +}; 880 847 + 848 +#define __GEN_SPI_RSET_BASE(__cpu, __rset) \ 849 + case SPI_## __rset: \ 850 + return SPI_BCM_## __cpu ##_SPI_## __rset ##; 851 + 852 +#define __GEN_SPI_RSET(__cpu) \ 853 + switch (reg) { \ 854 + __GEN_SPI_RSET_BASE(__cpu, CMD) \ 855 + __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \ 856 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \ 857 + __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \ 858 + __GEN_SPI_RSET_BASE(__cpu, ST) \ 859 + __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \ 860 + __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \ 861 + __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \ 862 + __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \ 863 + __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \ 864 + __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \ 865 + __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \ 866 + } 867 + 868 +#define __GEN_SPI_REGS_TABLE(__cpu) \ 869 + [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \ 870 + [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \ 871 + [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \ 872 + [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \ 873 + [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \ 874 + [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \ 875 + [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \ 876 + [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \ 877 + [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \ 878 + [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \ 879 + [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \ 880 + [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA, 881 + 881 882 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) 882 883 +{ … … 886 887 +#else 887 888 +#ifdef CONFIG_BCM63XX_CPU_6338 888 +switch (reg) { 889 + case SPI_CMD: 890 + return SPI_BCM_6338_SPI_CMD; 891 + case SPI_INT_STATUS: 892 + return SPI_BCM_6338_SPI_INT_STATUS; 893 + case SPI_INT_MASK_ST: 894 + return SPI_BCM_6338_SPI_MASK_INT_ST; 895 + case SPI_INT_MASK: 896 + return SPI_BCM_6338_SPI_INT_MASK; 897 + case SPI_ST: 898 + return SPI_BCM_6338_SPI_ST; 899 + case SPI_CLK_CFG: 900 + return SPI_BCM_6338_SPI_CLK_CFG; 901 + case SPI_FILL_BYTE: 902 + return SPI_BCM_6338_SPI_FILL_BYTE; 903 + case SPI_MSG_TAIL: 904 + return SPI_BCM_6338_SPI_MSG_TAIL; 905 + case SPI_RX_TAIL: 906 + return SPI_BCM_6338_SPI_RX_TAIL; 907 + case SPI_MSG_CTL: 908 + return SPI_BCM_6338_SPI_MSG_CTL; 909 + case SPI_MSG_DATA: 910 + return SPI_BCM_6338_SPI_MSG_DATA; 911 + case SPI_RX_DATA: 912 + return SPI_BCM_6338_SPI_RX_DATA; 913 +} 889 + __GEN_SPI_RSET(6338) 914 890 +#endif 915 891 +#ifdef CONFIG_BCM63XX_CPU_6348 916 +switch (reg) { 917 + case SPI_CMD: 918 + return SPI_BCM_6348_SPI_CMD; 919 + case SPI_INT_MASK_ST: 920 + return SPI_BCM_6348_SPI_MASK_INT_ST; 921 + case SPI_INT_MASK: 922 + return SPI_BCM_6348_SPI_INT_MASK; 923 + case SPI_INT_STATUS: 924 + return SPI_BCM_6348_SPI_INT_STATUS; 925 + case SPI_ST: 926 + return SPI_BCM_6348_SPI_ST; 927 + case SPI_CLK_CFG: 928 + return SPI_BCM_6348_SPI_CLK_CFG; 929 + case SPI_FILL_BYTE: 930 + return SPI_BCM_6348_SPI_FILL_BYTE; 931 + case SPI_MSG_TAIL: 932 + return SPI_BCM_6348_SPI_MSG_TAIL; 933 + case SPI_RX_TAIL: 934 + return SPI_BCM_6348_SPI_RX_TAIL; 935 + case SPI_MSG_CTL: 936 + return SPI_BCM_6348_SPI_MSG_CTL; 937 + case SPI_MSG_DATA: 938 + return SPI_BCM_6348_SPI_MSG_DATA; 939 + case SPI_RX_DATA: 940 + return SPI_BCM_6348_SPI_RX_DATA; 941 +} 892 + __GEN_SPI_RSET(6348) 942 893 +#endif 943 894 +#ifdef CONFIG_BCM63XX_CPU_6358 944 +switch (reg) { 945 + case SPI_CMD: 946 + return SPI_BCM_6358_SPI_CMD; 947 + case SPI_INT_STATUS: 948 + return SPI_BCM_6358_SPI_INT_STATUS; 949 + case SPI_INT_MASK_ST: 950 + return SPI_BCM_6358_SPI_MASK_INT_ST; 951 + case SPI_INT_MASK: 952 + return SPI_BCM_6358_SPI_INT_MASK; 953 + case SPI_ST: 954 + return SPI_BCM_6358_SPI_STATUS; 955 + case SPI_CLK_CFG: 956 + return SPI_BCM_6358_SPI_CLK_CFG; 957 + case SPI_FILL_BYTE: 958 + return SPI_BCM_6358_SPI_FILL_BYTE; 959 + case SPI_MSG_TAIL: 960 + return SPI_BCM_6358_SPI_MSG_TAIL; 961 + case SPI_RX_TAIL: 962 + return SPI_BCM_6358_SPI_RX_TAIL; 963 + case SPI_MSG_CTL: 964 + return SPI_BCM_6358_MSG_CTL; 965 + case SPI_MSG_DATA: 966 + return SPI_BCM_6358_SPI_MSG_DATA; 967 + case SPI_RX_DATA: 968 + return SPI_BCM_6358_SPI_RX_DATA; 969 +} 895 + __GEN_SPI_RSET(6358) 970 896 +#endif 971 897 +#endif
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