Changeset 26561


Ignore:
Timestamp:
2011-04-09T20:47:52+02:00 (7 years ago)
Author:
juhosg
Message:

ar71xx: rename ar934x_ref_freq to ar71xx_ref_freq

Also initialize that for each SoC and print its value along with the
other frequencies.

Location:
trunk/target/linux/ar71xx/files
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

    r26511 r26561  
    7575        case AR71XX_SOC_AR9342: 
    7676        case AR71XX_SOC_AR9344: 
    77                 ar71xx_uart_data[0].uartclk = ar934x_ref_freq; 
     77                ar71xx_uart_data[0].uartclk = ar71xx_ref_freq; 
    7878                break; 
    7979 
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

    r26560 r26561  
    2929 
    3030#define AR71XX_SYS_TYPE_LEN     64 
    31 #define AR71XX_BASE_FREQ        40000000 
    32 #define AR91XX_BASE_FREQ        5000000 
    33 #define AR724X_BASE_FREQ        5000000 
    3431 
    3532u32 ar71xx_cpu_freq; 
     
    4239EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); 
    4340 
    44 u32 ar934x_ref_freq; 
    45 EXPORT_SYMBOL_GPL(ar934x_ref_freq); 
     41u32 ar71xx_ref_freq; 
     42EXPORT_SYMBOL_GPL(ar71xx_ref_freq); 
    4643 
    4744enum ar71xx_soc_type ar71xx_soc; 
     
    175172static void __init ar934x_detect_sys_frequency(void) 
    176173{ 
    177         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv; 
     174        u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 
    178175 
    179176        if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) 
    180                 ref = (40 * 1000000); 
     177                ar71xx_ref_freq = 40 * 1000 * 1000; 
    181178        else 
    182                 ref = (25 * 1000000); 
    183  
    184         ar934x_ref_freq = ref; 
     179                ar71xx_ref_freq = 25 * 1000 * 1000; 
    185180 
    186181        clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); 
     
    192187        frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); 
    193188        postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); 
    194         ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1); 
     189        ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / 
     190                          (postdiv + 1); 
    195191 
    196192        out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); 
     
    199195        frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); 
    200196        postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); 
    201         ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1); 
     197        ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / 
     198                          (postdiv + 1); 
    202199 
    203200        postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); 
     
    217214        u32 div; 
    218215 
     216        ar71xx_ref_freq = 5 * 1000 * 1000; 
     217 
    219218        pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); 
    220219 
    221220        div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); 
    222         freq = div * AR91XX_BASE_FREQ; 
     221        freq = div * ar71xx_ref_freq; 
    223222 
    224223        ar71xx_cpu_freq = freq; 
     
    237236        u32 div; 
    238237 
     238        ar71xx_ref_freq = 40 * 1000 * 1000; 
     239 
    239240        pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 
    240241 
    241242        div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 
    242         freq = div * AR71XX_BASE_FREQ; 
     243        freq = div * ar71xx_ref_freq; 
    243244 
    244245        div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 
     
    258259        u32 div; 
    259260 
     261        ar71xx_ref_freq = 5 * 1000 * 1000; 
     262 
    260263        pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); 
    261264 
    262265        div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); 
    263         freq = div * AR724X_BASE_FREQ; 
     266        freq = div * ar71xx_ref_freq; 
    264267 
    265268        div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); 
     
    337340        detect_sys_frequency(); 
    338341 
    339         pr_info("Clocks: CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n", 
     342        pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, " 
     343                "Ref:%u.%03uMHz", 
    340344                ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, 
     345                ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000, 
    341346                ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, 
    342                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000); 
     347                ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000); 
    343348 
    344349        _machine_restart = ar71xx_restart; 
  • trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

    r26521 r26561  
    116116extern u32 ar71xx_cpu_freq; 
    117117extern u32 ar71xx_ddr_freq; 
    118 extern u32 ar934x_ref_freq; 
     118extern u32 ar71xx_ref_freq; 
    119119 
    120120enum ar71xx_soc_type { 
  • trunk/target/linux/ar71xx/files/drivers/watchdog/ar71xx_wdt.c

    r26516 r26561  
    223223        case AR71XX_SOC_AR9342: 
    224224        case AR71XX_SOC_AR9344: 
    225                 wdt_clk_freq = ar934x_ref_freq; 
     225                wdt_clk_freq = ar71xx_ref_freq; 
    226226                break; 
    227227 
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