Changeset 26509


Ignore:
Timestamp:
2011-04-07T22:52:45+02:00 (7 years ago)
Author:
juhosg
Message:

ar71xx: add initial support for the AR934x SoCs

Signed-off-by: Jaiganesh Narayanan <jnarayanan@…>

Location:
trunk/target/linux/ar71xx/files/arch/mips
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

    r23975 r26509  
    22 *  Atheros AR71xx SoC specific setup 
    33 * 
     4 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 
    45 *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> 
    56 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 
    67 * 
    7  *  Parts of this file are based on Atheros' 2.6.15 BSP 
     8 *  Parts of this file are based on Atheros 2.6.15 BSP 
     9 *  Parts of this file are based on Atheros 2.6.31 BSP 
    810 * 
    911 *  This program is free software; you can redistribute it and/or modify it 
     
    3941u32 ar71xx_ddr_freq; 
    4042EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); 
     43 
     44u32 ar934x_ref_freq; 
     45EXPORT_SYMBOL_GPL(ar934x_ref_freq); 
    4146 
    4247enum ar71xx_soc_type ar71xx_soc; 
     
    142147                break; 
    143148 
     149        case REV_ID_MAJOR_AR9341: 
     150                ar71xx_soc = AR71XX_SOC_AR9341; 
     151                chip = "9341"; 
     152                rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & 
     153                        AR934X_REV_ID_REVISION_MASK; 
     154                break; 
     155 
     156        case REV_ID_MAJOR_AR9342: 
     157                ar71xx_soc = AR71XX_SOC_AR9342; 
     158                chip = "9342"; 
     159                rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & 
     160                        AR934X_REV_ID_REVISION_MASK; 
     161                break; 
     162 
     163        case REV_ID_MAJOR_AR9344: 
     164                ar71xx_soc = AR71XX_SOC_AR9344; 
     165                chip = "9344"; 
     166                rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & 
     167                        AR934X_REV_ID_REVISION_MASK; 
     168                break; 
     169 
    144170        default: 
    145171                panic("ar71xx: unknown chip id:0x%08x\n", id); 
     
    147173 
    148174        sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); 
     175} 
     176 
     177static void __init ar934x_detect_sys_frequency(void) 
     178{ 
     179        u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv; 
     180 
     181        if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) 
     182                ref = (40 * 1000000); 
     183        else 
     184                ref = (25 * 1000000); 
     185 
     186        ar934x_ref_freq = ref; 
     187 
     188        clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); 
     189 
     190        pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); 
     191        out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll); 
     192        ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll); 
     193        nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll); 
     194        frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); 
     195        postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); 
     196        ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1); 
     197 
     198        out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); 
     199        ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); 
     200        nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll); 
     201        frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); 
     202        postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); 
     203        ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1); 
     204 
     205        postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); 
     206 
     207        if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { 
     208                ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1); 
     209        } else { 
     210                ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); 
     211        } 
     212 
    149213} 
    150214 
     
    233297                break; 
    234298 
     299        case AR71XX_SOC_AR9341: 
     300        case AR71XX_SOC_AR9342: 
     301        case AR71XX_SOC_AR9344: 
     302                ar934x_detect_sys_frequency(); 
     303                break; 
    235304        default: 
    236305                BUG(); 
  • trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

    r23135 r26509  
    22 *  Atheros AR71xx SoC specific definitions 
    33 * 
     4 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 
    45 *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> 
    56 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 
    67 * 
    7  *  Parts of this file are based on Atheros' 2.6.15 BSP 
     8 *  Parts of this file are based on Atheros 2.6.15 BSP 
     9 *  Parts of this file are based on Atheros 2.6.31 BSP 
    810 * 
    911 *  This program is free software; you can redistribute it and/or modify it 
     
    106108extern u32 ar71xx_cpu_freq; 
    107109extern u32 ar71xx_ddr_freq; 
     110extern u32 ar934x_ref_freq; 
    108111 
    109112enum ar71xx_soc_type { 
     
    116119        AR71XX_SOC_AR7242, 
    117120        AR71XX_SOC_AR9130, 
    118         AR71XX_SOC_AR9132 
     121        AR71XX_SOC_AR9132, 
     122        AR71XX_SOC_AR9341, 
     123        AR71XX_SOC_AR9342, 
     124        AR71XX_SOC_AR9344, 
    119125}; 
    120126 
     
    167173#define AR91XX_ETH0_PLL_SHIFT           20 
    168174#define AR91XX_ETH1_PLL_SHIFT           22 
     175 
     176#define AR934X_PLL_REG_CPU_CONFIG       0x00 
     177#define AR934X_PLL_REG_DDR_CTRL_CLOCK   0x8 
     178 
     179#define AR934X_CPU_PLL_CFG_OUTDIV_MSB   21 
     180#define AR934X_CPU_PLL_CFG_OUTDIV_LSB   19 
     181#define AR934X_CPU_PLL_CFG_OUTDIV_MASK  0x00380000 
     182 
     183#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x)                \ 
     184        (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >>      \ 
     185        AR934X_CPU_PLL_CFG_OUTDIV_LSB) 
     186 
     187#define AR934X_DDR_PLL_CFG_OUTDIV_MSB   25 
     188#define AR934X_DDR_PLL_CFG_OUTDIV_LSB   23 
     189#define AR934X_DDR_PLL_CFG_OUTDIV_MASK  0x03800000 
     190 
     191#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x)                \ 
     192        (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >>      \ 
     193        AR934X_DDR_PLL_CFG_OUTDIV_LSB) 
     194 
     195#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x)                \ 
     196        (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) &       \ 
     197        AR934X_DDR_PLL_CFG_OUTDIV_MASK) 
     198 
     199#define AR934X_CPU_PLL_CFG_REFDIV_MSB   16 
     200#define AR934X_CPU_PLL_CFG_REFDIV_LSB   12 
     201#define AR934X_CPU_PLL_CFG_REFDIV_MASK  0x0001f000 
     202 
     203#define AR934X_CPU_PLL_CFG_REFDIV_GET(x)                \ 
     204        (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >>      \ 
     205        AR934X_CPU_PLL_CFG_REFDIV_LSB) 
     206 
     207#define AR934X_CPU_PLL_CFG_REFDIV_SET(x)                \ 
     208        (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) &       \ 
     209        AR934X_CPU_PLL_CFG_REFDIV_MASK) 
     210 
     211#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2 
     212 
     213#define AR934X_CPU_PLL_CFG_NINT_MSB     11 
     214#define AR934X_CPU_PLL_CFG_NINT_LSB     6 
     215#define AR934X_CPU_PLL_CFG_NINT_MASK    0x00000fc0 
     216 
     217#define AR934X_CPU_PLL_CFG_NINT_GET(x)                  \ 
     218        (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >>        \ 
     219        AR934X_CPU_PLL_CFG_NINT_LSB) 
     220 
     221#define AR934X_CPU_PLL_CFG_NINT_SET(x)                  \ 
     222        (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) &         \ 
     223        AR934X_CPU_PLL_CFG_NINT_MASK) 
     224 
     225#define AR934X_CPU_PLL_CFG_NINT_RESET   20 
     226 
     227#define AR934X_CPU_PLL_CFG_NFRAC_MSB    5 
     228#define AR934X_CPU_PLL_CFG_NFRAC_LSB    0 
     229#define AR934X_CPU_PLL_CFG_NFRAC_MASK   0x0000003f 
     230 
     231#define AR934X_CPU_PLL_CFG_NFRAC_GET(x)         \ 
     232        (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >>       \ 
     233        AR934X_CPU_PLL_CFG_NFRAC_LSB) 
     234 
     235#define AR934X_CPU_PLL_CFG_NFRAC_SET(x)         \ 
     236        (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) &        \ 
     237        AR934X_CPU_PLL_CFG_NFRAC_MASK) 
     238 
     239#define AR934X_DDR_PLL_CFG_REFDIV_MSB   20 
     240#define AR934X_DDR_PLL_CFG_REFDIV_LSB   16 
     241#define AR934X_DDR_PLL_CFG_REFDIV_MASK  0x001f0000 
     242 
     243#define AR934X_DDR_PLL_CFG_REFDIV_GET(x)                \ 
     244        (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >>      \ 
     245        AR934X_DDR_PLL_CFG_REFDIV_LSB) 
     246 
     247#define AR934X_DDR_PLL_CFG_REFDIV_SET(x)                \ 
     248        (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) &       \ 
     249        AR934X_DDR_PLL_CFG_REFDIV_MASK) 
     250 
     251#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2 
     252 
     253#define AR934X_DDR_PLL_CFG_NINT_MSB     15 
     254#define AR934X_DDR_PLL_CFG_NINT_LSB     10 
     255#define AR934X_DDR_PLL_CFG_NINT_MASK    0x0000fc00 
     256 
     257#define AR934X_DDR_PLL_CFG_NINT_GET(x)                  \ 
     258        (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >>        \ 
     259        AR934X_DDR_PLL_CFG_NINT_LSB) 
     260 
     261#define AR934X_DDR_PLL_CFG_NINT_SET(x)                  \ 
     262        (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) &         \ 
     263        AR934X_DDR_PLL_CFG_NINT_MASK) 
     264 
     265#define AR934X_DDR_PLL_CFG_NINT_RESET   20 
     266 
     267#define AR934X_DDR_PLL_CFG_NFRAC_MSB    9 
     268#define AR934X_DDR_PLL_CFG_NFRAC_LSB    0 
     269#define AR934X_DDR_PLL_CFG_NFRAC_MASK   0x000003ff 
     270 
     271#define AR934X_DDR_PLL_CFG_NFRAC_GET(x)         \ 
     272        (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >>       \ 
     273        AR934X_DDR_PLL_CFG_NFRAC_LSB) 
     274 
     275#define AR934X_DDR_PLL_CFG_NFRAC_SET(x)         \ 
     276        (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) &        \ 
     277        AR934X_DDR_PLL_CFG_NFRAC_MASK) 
     278 
     279#define AR934X_DDR_PLL_CFG_NFRAC_RESET  512 
     280 
     281#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB        19 
     282#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB        15 
     283#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK       0x000f8000 
     284 
     285#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x)             \ 
     286        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >>   \ 
     287        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) 
     288 
     289#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x)             \ 
     290        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) &    \ 
     291        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) 
     292 
     293#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET              0 
     294 
     295#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB        14 
     296#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB        10 
     297#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK       0x00007c00 
     298 
     299#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x)             \ 
     300        (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >>   \ 
     301        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) 
     302 
     303#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x)             \ 
     304        (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) &    \ 
     305        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) 
     306 
     307#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET      0 
     308 
     309#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB        9 
     310#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB        5 
     311#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK       0x000003e0 
     312 
     313#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x)             \ 
     314        (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >>   \ 
     315        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) 
     316 
     317#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x)             \ 
     318        (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) &    \ 
     319        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) 
     320 
     321#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET      0 
     322 
     323#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB  24 
     324#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB  24 
     325#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 
     326 
     327#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x)       \ 
     328        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \ 
     329        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) 
     330 
     331#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x)       \ 
     332        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \ 
     333        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) 
     334 
     335#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET        1 
    169336 
    170337extern void __iomem *ar71xx_pll_base; 
     
    385552 
    386553#define AR724X_RESET_REG_RESET_MODULE           0x1c 
     554 
     555#define AR934X_RESET_REG_RESET_MODULE           0x1c 
     556#define AR934X_RESET_REG_BOOTSTRAP              0xb0 
     557/* 0 - 25MHz   1 - 40 MHz */ 
     558#define AR934X_REF_CLK_40                       (1 << 4) 
    387559 
    388560#define WDOG_CTRL_LAST_RESET            BIT(31) 
     
    443615#define REV_ID_MAJOR_AR7241     0x0100 
    444616#define REV_ID_MAJOR_AR7242     0x1100 
     617#define REV_ID_MAJOR_AR9341     0x0120 
     618#define REV_ID_MAJOR_AR9342     0x1120 
     619#define REV_ID_MAJOR_AR9344     0x2120 
    445620 
    446621#define AR71XX_REV_ID_MINOR_MASK        0x3 
     
    458633 
    459634#define AR724X_REV_ID_REVISION_MASK     0x3 
     635 
     636#define AR934X_REV_ID_REVISION_MASK     0xf 
    460637 
    461638extern void __iomem *ar71xx_reset_base; 
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