Changeset 26326
- Timestamp:
- 2011-03-27T21:19:59+02:00 (7 years ago)
- Location:
- trunk/target/linux/ramips/files/arch/mips
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h
r17454 r26326 16 16 #define RALINK_SOC_MEM_SIZE_MAX (128 * 1024 * 1024) 17 17 18 #define RALINK_SOC_GPIO_BASE 0x30060019 20 #define RALINK_SOC_GPIO0_COUNT 2421 #define RALINK_SOC_GPIO1_COUNT 1622 #define RALINK_SOC_GPIO2_COUNT 3223 24 18 #endif /* __RT288X_RALINK_SOC_H */ -
trunk/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
r25129 r26326 38 38 #define RT2880_MEMC_SIZE 0x100 39 39 #define RT2880_UART0_SIZE 0x100 40 #define RT2880_PIO_SIZE 0x100 40 41 #define RT2880_UART1_SIZE 0x100 41 42 #define RT2880_FLASH1_SIZE (16 * 1024 * 1024) -
trunk/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h
r17454 r26326 16 16 #define RALINK_SOC_MEM_SIZE_MAX (64 * 1024 * 1024) 17 17 18 #define RALINK_SOC_GPIO_BASE 0x1000060019 20 #define RALINK_SOC_GPIO0_COUNT 2421 #define RALINK_SOC_GPIO1_COUNT 1622 #define RALINK_SOC_GPIO2_COUNT 1223 24 18 #endif /* __RT288X_RALINK_SOC_H */ -
trunk/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
r25127 r26326 21 21 #define RT305X_PCM_BASE 0x10000400 22 22 #define RT305X_UART0_BASE 0x10000500 23 #define RT305X_PIO_BASE 0x10000600 23 24 #define RT305X_GDMA_BASE 0x10000700 24 25 #define RT305X_NANDC_BASE 0x10000800 … … 40 41 #define RT305X_MEMC_SIZE 0x100 41 42 #define RT305X_UART0_SIZE 0x100 43 #define RT305X_PIO_SIZE 0x100 42 44 #define RT305X_UART1_SIZE 0x100 43 45 #define RT305X_FLASH1_SIZE (16 * 1024 * 1024) -
trunk/target/linux/ramips/files/arch/mips/ralink/common/gpio.c
r26325 r26326 87 87 } 88 88 89 static struct ramips_gpio_chip ramips_gpio_chip0 = {90 .chip = {91 .label = "ramips-gpio0",92 .base = 0,93 .ngpio = RALINK_SOC_GPIO0_COUNT,94 },95 .regs = {96 [RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,97 [RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,98 [RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,99 [RAMIPS_GPIO_REG_FENA] = GPIO0_REG_FENA,100 [RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,101 [RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,102 [RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,103 [RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,104 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,105 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,106 },107 .map_base = RALINK_SOC_GPIO_BASE,108 .map_size = PAGE_SIZE,109 };110 111 static struct ramips_gpio_chip ramips_gpio_chip1 = {112 .chip = {113 .label = "ramips-gpio1",114 .base = 32,115 .ngpio = RALINK_SOC_GPIO1_COUNT,116 },117 .regs = {118 [RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,119 [RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,120 [RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,121 [RAMIPS_GPIO_REG_FENA] = GPIO1_REG_FENA,122 [RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,123 [RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,124 [RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,125 [RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,126 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,127 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,128 },129 .map_base = RALINK_SOC_GPIO_BASE,130 .map_size = PAGE_SIZE,131 };132 133 static struct ramips_gpio_chip ramips_gpio_chip2 = {134 .chip = {135 .label = "ramips-gpio2",136 .base = 64,137 .ngpio = RALINK_SOC_GPIO2_COUNT,138 },139 .regs = {140 [RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,141 [RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,142 [RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,143 [RAMIPS_GPIO_REG_FENA] = GPIO2_REG_FENA,144 [RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,145 [RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,146 [RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,147 [RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,148 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,149 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,150 },151 .map_base = RALINK_SOC_GPIO_BASE,152 .map_size = PAGE_SIZE,153 };154 155 89 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) 156 90 { … … 170 104 } 171 105 172 __init int ramips_gpio_init( void)106 __init int ramips_gpio_init(struct ramips_gpio_data *data) 173 107 { 174 ramips_gpio_chip_add(&ramips_gpio_chip0); 175 ramips_gpio_chip_add(&ramips_gpio_chip1); 176 ramips_gpio_chip_add(&ramips_gpio_chip2); 108 int i; 109 110 for (i = 0; i < data->num_chips; i++) 111 ramips_gpio_chip_add(&data->chips[i]); 177 112 178 113 return 0; -
trunk/target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c
r26325 r26326 44 44 } 45 45 46 static struct ramips_gpio_chip rt288x_gpio_chips[] = { 47 { 48 .chip = { 49 .label = "RT288X-GPIO0", 50 .base = 0, 51 .ngpio = 24, 52 }, 53 .regs = { 54 [RAMIPS_GPIO_REG_INT] = 0x00, 55 [RAMIPS_GPIO_REG_EDGE] = 0x04, 56 [RAMIPS_GPIO_REG_RENA] = 0x08, 57 [RAMIPS_GPIO_REG_FENA] = 0x0c, 58 [RAMIPS_GPIO_REG_DATA] = 0x20, 59 [RAMIPS_GPIO_REG_DIR] = 0x24, 60 [RAMIPS_GPIO_REG_POL] = 0x28, 61 [RAMIPS_GPIO_REG_SET] = 0x2c, 62 [RAMIPS_GPIO_REG_RESET] = 0x30, 63 [RAMIPS_GPIO_REG_TOGGLE] = 0x34, 64 }, 65 .map_base = RT2880_PIO_BASE, 66 .map_size = RT2880_PIO_SIZE, 67 }, 68 { 69 .chip = { 70 .label = "RT288X-GPIO1", 71 .base = 24, 72 .ngpio = 16, 73 }, 74 .regs = { 75 [RAMIPS_GPIO_REG_INT] = 0x38, 76 [RAMIPS_GPIO_REG_EDGE] = 0x3c, 77 [RAMIPS_GPIO_REG_RENA] = 0x40, 78 [RAMIPS_GPIO_REG_FENA] = 0x44, 79 [RAMIPS_GPIO_REG_DATA] = 0x48, 80 [RAMIPS_GPIO_REG_DIR] = 0x4c, 81 [RAMIPS_GPIO_REG_POL] = 0x50, 82 [RAMIPS_GPIO_REG_SET] = 0x54, 83 [RAMIPS_GPIO_REG_RESET] = 0x58, 84 [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, 85 }, 86 .map_base = RT2880_PIO_BASE, 87 .map_size = RT2880_PIO_SIZE, 88 }, 89 { 90 .chip = { 91 .label = "RT288X-GPIO2", 92 .base = 40, 93 .ngpio = 32, 94 }, 95 .regs = { 96 [RAMIPS_GPIO_REG_INT] = 0x60, 97 [RAMIPS_GPIO_REG_EDGE] = 0x64, 98 [RAMIPS_GPIO_REG_RENA] = 0x68, 99 [RAMIPS_GPIO_REG_FENA] = 0x6c, 100 [RAMIPS_GPIO_REG_DATA] = 0x70, 101 [RAMIPS_GPIO_REG_DIR] = 0x74, 102 [RAMIPS_GPIO_REG_POL] = 0x78, 103 [RAMIPS_GPIO_REG_SET] = 0x7c, 104 [RAMIPS_GPIO_REG_RESET] = 0x80, 105 [RAMIPS_GPIO_REG_TOGGLE] = 0x84, 106 }, 107 .map_base = RT2880_PIO_BASE, 108 .map_size = RT2880_PIO_SIZE, 109 }, 110 }; 111 112 static struct ramips_gpio_data rt288x_gpio_data = { 113 .chips = rt288x_gpio_chips, 114 .num_chips = ARRAY_SIZE(rt288x_gpio_chips), 115 }; 116 46 117 static void rt288x_gpio_reserve(int first, int last) 47 118 { … … 54 125 rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE); 55 126 56 ramips_gpio_init( );127 ramips_gpio_init(&rt288x_gpio_data); 57 128 if ((mode & RT2880_GPIO_MODE_I2C) == 0) 58 129 rt288x_gpio_reserve(1, 2); -
trunk/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
r26325 r26326 44 44 } 45 45 46 static struct ramips_gpio_chip rt305x_gpio_chips[] = { 47 { 48 .chip = { 49 .label = "RT305X-GPIO0", 50 .base = 0, 51 .ngpio = 24, 52 }, 53 .regs = { 54 [RAMIPS_GPIO_REG_INT] = 0x00, 55 [RAMIPS_GPIO_REG_EDGE] = 0x04, 56 [RAMIPS_GPIO_REG_RENA] = 0x08, 57 [RAMIPS_GPIO_REG_FENA] = 0x0c, 58 [RAMIPS_GPIO_REG_DATA] = 0x20, 59 [RAMIPS_GPIO_REG_DIR] = 0x24, 60 [RAMIPS_GPIO_REG_POL] = 0x28, 61 [RAMIPS_GPIO_REG_SET] = 0x2c, 62 [RAMIPS_GPIO_REG_RESET] = 0x30, 63 [RAMIPS_GPIO_REG_TOGGLE] = 0x34, 64 }, 65 .map_base = RT305X_PIO_BASE, 66 .map_size = RT305X_PIO_SIZE, 67 }, 68 { 69 .chip = { 70 .label = "RT305X-GPIO1", 71 .base = 24, 72 .ngpio = 16, 73 }, 74 .regs = { 75 [RAMIPS_GPIO_REG_INT] = 0x38, 76 [RAMIPS_GPIO_REG_EDGE] = 0x3c, 77 [RAMIPS_GPIO_REG_RENA] = 0x40, 78 [RAMIPS_GPIO_REG_FENA] = 0x44, 79 [RAMIPS_GPIO_REG_DATA] = 0x48, 80 [RAMIPS_GPIO_REG_DIR] = 0x4c, 81 [RAMIPS_GPIO_REG_POL] = 0x50, 82 [RAMIPS_GPIO_REG_SET] = 0x54, 83 [RAMIPS_GPIO_REG_RESET] = 0x58, 84 [RAMIPS_GPIO_REG_TOGGLE] = 0x5c, 85 }, 86 .map_base = RT305X_PIO_BASE, 87 .map_size = RT305X_PIO_SIZE, 88 }, 89 { 90 .chip = { 91 .label = "RT305X-GPIO2", 92 .base = 40, 93 .ngpio = 12, 94 }, 95 .regs = { 96 [RAMIPS_GPIO_REG_INT] = 0x60, 97 [RAMIPS_GPIO_REG_EDGE] = 0x64, 98 [RAMIPS_GPIO_REG_RENA] = 0x68, 99 [RAMIPS_GPIO_REG_FENA] = 0x6c, 100 [RAMIPS_GPIO_REG_DATA] = 0x70, 101 [RAMIPS_GPIO_REG_DIR] = 0x74, 102 [RAMIPS_GPIO_REG_POL] = 0x78, 103 [RAMIPS_GPIO_REG_SET] = 0x7c, 104 [RAMIPS_GPIO_REG_RESET] = 0x80, 105 [RAMIPS_GPIO_REG_TOGGLE] = 0x84, 106 }, 107 .map_base = RT305X_PIO_BASE, 108 .map_size = RT305X_PIO_SIZE, 109 }, 110 }; 111 112 static struct ramips_gpio_data rt305x_gpio_data = { 113 .chips = rt305x_gpio_chips, 114 .num_chips = ARRAY_SIZE(rt305x_gpio_chips), 115 }; 116 46 117 static void rt305x_gpio_reserve(int first, int last) 47 118 { … … 56 127 rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE); 57 128 58 ramips_gpio_init( );129 ramips_gpio_init(&rt305x_gpio_data); 59 130 if ((mode & RT305X_GPIO_MODE_I2C) == 0) 60 131 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
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