Ticket #6185: trunk-titan.patch
| File trunk-titan.patch, 23.8 KB (added by Xin Zhen (LoneStar) <xlonestar2000@…>, 8 years ago) |
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target/linux/ar7/files/include/asm-mips/ar7/ar7.h
44 44 #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 45 45 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 46 46 47 #define TITAN_REGS_MAC0 (0x08640000) 48 #define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800) 49 #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) 50 #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) 51 47 52 #define AR7_RESET_PEREPHERIAL 0x0 48 53 #define AR7_RESET_SOFTWARE 0x4 49 54 #define AR7_RESET_STATUS 0x8 … … 53 58 #define AR7_RESET_BIT_MDIO 22 54 59 #define AR7_RESET_BIT_EPHY 26 55 60 61 #define TITAN_RESET_BIT_EPHY1 28 62 56 63 /* GPIO control registers */ 57 64 #define AR7_GPIO_INPUT 0x0 58 65 #define AR7_GPIO_OUTPUT 0x4 59 66 #define AR7_GPIO_DIR 0x8 60 67 #define AR7_GPIO_ENABLE 0xc 68 #define TITAN_GPIO_INPUT_0 0x0 69 #define TITAN_GPIO_INPUT_1 0x4 70 #define TITAN_GPIO_OUTPUT_0 0x8 71 #define TITAN_GPIO_OUTPUT_1 0xc 72 #define TITAN_GPIO_DIR_0 0x10 73 #define TITAN_GPIO_DIR_1 0x14 74 #define TITAN_GPIO_ENBL_0 0x18 75 #define TITAN_GPIO_ENBL_1 0x1c 61 76 62 77 #define AR7_CHIP_7100 0x18 63 78 #define AR7_CHIP_7200 0x2b 64 79 #define AR7_CHIP_7300 0x05 80 #define AR7_CHIP_TITAN 0x07 81 #define TITAN_CHIP_1050 0x0f 82 #define TITAN_CHIP_1055 0x0e 83 #define TITAN_CHIP_1056 0x0d 84 #define TITAN_CHIP_1060 0x07 65 85 66 86 /* Interrupts */ 67 87 #define AR7_IRQ_UART0 15 … … 86 106 87 107 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; 88 108 109 static inline int ar7_is_titan(void) 110 { 111 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == 112 AR7_CHIP_TITAN; 113 } 114 89 115 static inline u16 ar7_chip_id(void) 90 116 { 91 return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; 117 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) 118 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); 92 119 } 93 120 94 121 static inline u8 ar7_chip_rev(void) 95 122 { 96 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; 123 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : 124 0x14))) >> 16) & 0xff; 97 125 } 98 126 99 127 static inline int ar7_cpu_freq(void) -
target/linux/ar7/files/include/asm-mips/ar7/gpio.h
19 19 #ifndef __AR7_GPIO_H__ 20 20 #define __AR7_GPIO_H__ 21 21 #include <asm/ar7/ar7.h> 22 #ifndef __AR7_TITAN_H__ 23 #include <asm/ar7/titan.h> 24 #endif 22 25 23 26 #define AR7_GPIO_MAX 32 27 #define TITAN_GPIO_MAX 51 24 28 25 29 extern int gpio_request(unsigned gpio, const char *label); 26 30 extern void gpio_free(unsigned gpio); 27 31 28 32 /* Common GPIO layer */ 29 static inline int gpio_get_value (unsigned gpio)33 static inline int gpio_get_value_ar7(unsigned gpio) 30 34 { 31 35 void __iomem *gpio_in = 32 36 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT); … … 34 38 return readl(gpio_in) & (1 << gpio); 35 39 } 36 40 37 static inline void gpio_set_value(unsigned gpio, int value)41 static inline int gpio_get_value_titan(unsigned gpio) 38 42 { 43 void __iomem *gpio_in0 = 44 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); 45 void __iomem *gpio_in1 = 46 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1); 47 48 return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); 49 } 50 51 static inline int gpio_get_value(unsigned gpio) 52 { 53 return ar7_is_titan() ? gpio_get_value_titan(gpio) : 54 gpio_get_value_ar7(gpio); 55 } 56 57 static inline void gpio_set_value_ar7(unsigned gpio, int value) 58 { 39 59 void __iomem *gpio_out = 40 60 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT); 41 61 unsigned tmp; … … 46 66 writel(tmp, gpio_out); 47 67 } 48 68 49 static inline int gpio_direction_input(unsigned gpio)69 static inline void gpio_set_value_titan(unsigned gpio, int value) 50 70 { 71 void __iomem *gpio_out0 = 72 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0); 73 void __iomem *gpio_out1 = 74 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1); 75 unsigned tmp; 76 77 tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); 78 if (value) 79 tmp |= 1 << (gpio & 0x1f); 80 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); 81 } 82 83 static inline void gpio_set_value(unsigned gpio, int value) 84 { 85 if (ar7_is_titan()) 86 gpio_set_value_titan(gpio, value); 87 else 88 gpio_set_value_ar7(gpio, value); 89 } 90 91 static inline int gpio_direction_input_ar7(unsigned gpio) 92 { 51 93 void __iomem *gpio_dir = 52 94 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); 53 95 … … 59 101 return 0; 60 102 } 61 103 62 static inline int gpio_direction_ output(unsigned gpio, int value)104 static inline int gpio_direction_input_titan(unsigned gpio) 63 105 { 106 void __iomem *gpio_dir0 = 107 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0); 108 void __iomem *gpio_dir1 = 109 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1); 110 111 if (gpio >= TITAN_GPIO_MAX) 112 return -EINVAL; 113 114 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), 115 gpio >> 5 ? gpio_dir1 : gpio_dir0); 116 117 return 0; 118 } 119 120 static inline int gpio_direction_input(unsigned gpio) 121 { 122 return ar7_is_titan() ? gpio_direction_input_titan(gpio) : 123 gpio_direction_input_ar7(gpio); 124 } 125 126 static inline int gpio_direction_output_ar7(unsigned gpio, int value) 127 { 64 128 void __iomem *gpio_dir = 65 129 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); 66 130 … … 73 137 return 0; 74 138 } 75 139 140 static inline int gpio_direction_output_titan(unsigned gpio, int value) 141 { 142 void __iomem *gpio_dir0 = 143 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0); 144 void __iomem *gpio_dir1 = 145 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1); 146 147 if (gpio >= TITAN_GPIO_MAX) 148 return -EINVAL; 149 150 gpio_set_value_titan(gpio, value); 151 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << 152 (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0); 153 154 return 0; 155 } 156 157 static inline int gpio_direction_output(unsigned gpio, int value) 158 { 159 return ar7_is_titan() ? gpio_direction_output_titan(gpio, value) : 160 gpio_direction_output_ar7(gpio, value); 161 } 162 76 163 static inline int gpio_to_irq(unsigned gpio) 77 164 { 78 165 return -EINVAL; … … 84 171 } 85 172 86 173 /* Board specific GPIO functions */ 87 static inline int ar7_gpio_enable (unsigned gpio)174 static inline int ar7_gpio_enable_ar7(unsigned gpio) 88 175 { 89 176 void __iomem *gpio_en = 90 177 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); … … 94 181 return 0; 95 182 } 96 183 97 static inline int ar7_gpio_ disable(unsigned gpio)184 static inline int ar7_gpio_enable_titan(unsigned gpio) 98 185 { 186 void __iomem *gpio_en0 = 187 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0); 188 void __iomem *gpio_en1 = 189 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1); 190 191 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), 192 gpio >> 5 ? gpio_en1 : gpio_en0); 193 194 return 0; 195 } 196 197 static inline int ar7_gpio_enable(unsigned gpio) 198 { 199 return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) : 200 ar7_gpio_enable_ar7(gpio); 201 } 202 203 static inline int ar7_gpio_disable_ar7(unsigned gpio) 204 { 99 205 void __iomem *gpio_en = 100 206 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); 101 207 … … 104 210 return 0; 105 211 } 106 212 213 static inline int ar7_gpio_disable_titan(unsigned gpio) 214 { 215 void __iomem *gpio_en0 = 216 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0); 217 void __iomem *gpio_en1 = 218 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1); 219 220 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), 221 gpio >> 5 ? gpio_en1 : gpio_en0); 222 223 return 0; 224 } 225 226 static inline int ar7_gpio_disable(unsigned gpio) 227 { 228 return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) : 229 ar7_gpio_disable_ar7(gpio); 230 } 231 232 static inline int ar7_init_titan_variant( void ) 233 { 234 /*UINT32 new_val;*/ 235 unsigned new_val; 236 237 /* set GPIO 44 - 47 as input */ 238 /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */ 239 /*define titan_gpio_ctrl in titan.h*/ 240 titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN); 241 titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN); 242 titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN); 243 titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN); 244 245 /* read GPIO to get Titan variant type */ 246 /*fix this*/ 247 titan_sysGpioInValue( &new_val, 1 ); 248 249 new_val >>= 12; 250 new_val &= 0x0f; 251 252 switch ( new_val ) 253 { 254 case TITAN_CHIP_1050: 255 case TITAN_CHIP_1055: 256 case TITAN_CHIP_1056: 257 case TITAN_CHIP_1060: 258 return new_val; 259 260 default: 261 break; 262 } 263 /* In case we get an invalid value, return the default Titan chip */ 264 return TITAN_CHIP_1050; 265 } 266 107 267 #include <asm-generic/gpio.h> 108 268 109 269 #endif -
target/linux/ar7/files/include/asm-mips/ar7/titan.h
1 /* 2 * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 */ 18 #ifndef __AR7_TITAN_H__ 19 #define __AR7_TITAN_H__ 20 21 #ifndef __AR7_GPIO_H__ 22 #include <asm/ar7/gpio.h> 23 #endif 24 25 typedef enum TITAN_GPIO_PIN_MODE_tag 26 { 27 FUNCTIONAL_PIN = 0, 28 GPIO_PIN = 1 29 } TITAN_GPIO_PIN_MODE_T; 30 31 typedef enum TITAN_GPIO_PIN_DIRECTION_tag 32 { 33 GPIO_OUTPUT_PIN = 0, 34 GPIO_INPUT_PIN = 1 35 } TITAN_GPIO_PIN_DIRECTION_T; 36 37 /********************************************************************** 38 * GPIO Control 39 **********************************************************************/ 40 41 typedef struct 42 { 43 int pinSelReg; 44 int shift; 45 int func; 46 47 } GPIO_CFG; 48 49 static GPIO_CFG gptable[]= { 50 /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */ 51 {4,24,1}, 52 {4,26,1}, 53 {4,28,1}, 54 {4,30,1}, 55 {5,6,1}, 56 {5,8,1}, 57 {5,10,1}, 58 {5,12,1}, 59 {7,14,3}, 60 {7,16,3}, 61 {7,18,3}, 62 {7,20,3}, 63 {7,22,3}, 64 {7,26,3}, 65 {7,28,3}, 66 {7,30,3}, 67 {8,0,3}, 68 {8,2,3}, 69 {8,4,3}, 70 {8,10,3}, 71 {8,14,3}, 72 {8,16,3}, 73 {8,18,3}, 74 {8,20,3}, 75 {9,8,3}, 76 {9,10,3}, 77 {9,12,3}, 78 {9,14,3}, 79 {9,18,3}, 80 {9,20,3}, 81 {9,24,3}, 82 {9,26,3}, 83 {9,28,3}, 84 {9,30,3}, 85 {10,0,3}, 86 {10,2,3}, 87 {10,8,3}, 88 {10,10,3}, 89 {10,12,3}, 90 {10,14,3}, 91 {13,12,3}, 92 {13,14,3}, 93 {13,16,3}, 94 {13,18,3}, 95 {13,24,3}, 96 {13,26,3}, 97 {13,28,3}, 98 {13,30,3}, 99 {14,2,3}, 100 {14,6,3}, 101 {14,8,3}, 102 {14,12,3} 103 }; 104 105 typedef struct 106 { 107 volatile unsigned int reg[21]; 108 } 109 PIN_SEL_REG_ARRAY_T; 110 111 typedef struct 112 { 113 unsigned int data_in [2]; 114 unsigned int data_out[2]; 115 unsigned int dir[2]; 116 unsigned int enable[2]; 117 118 } TITAN_GPIO_CONTROL_T; 119 120 #define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/ 121 122 static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode, 123 TITAN_GPIO_PIN_DIRECTION_T pin_direction) 124 { 125 int reg_index = 0; 126 int mux_status; 127 GPIO_CFG gpio_cfg; 128 volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE; 129 volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); 130 131 if (gpio_pin > 51 ) 132 return(-1); 133 134 gpio_cfg = gptable[gpio_pin]; 135 mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3; 136 if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/))) 137 { 138 return(-1); /* Pin have been configured for non GPIO funcs. */ 139 } 140 141 /* Set the pin to be used as GPIO. */ 142 pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift); 143 144 /* Check whether gpio refers to the first GPIO reg or second. */ 145 if(gpio_pin > 31) 146 { 147 reg_index = 1; 148 gpio_pin -= 32; 149 } 150 151 if(pin_mode) 152 gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */ 153 else 154 gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin); 155 156 if(pin_direction) 157 gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */ 158 else 159 gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin); 160 161 return(0); 162 163 }/* end of function titan_gpio_ctrl */ 164 165 static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index) 166 { 167 volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0); 168 169 if(reg_index > 1) 170 return (-1); 171 172 *in_val = gpio_cntl->data_in[reg_index]; 173 174 return (0); 175 } 176 177 178 #endif -
target/linux/ar7/files/arch/mips/ar7/gpio.c
21 21 22 22 #include <asm/ar7/gpio.h> 23 23 24 static const char *ar7_gpio_list[ AR7_GPIO_MAX];24 static const char *ar7_gpio_list[TITAN_GPIO_MAX]; 25 25 26 26 int gpio_request(unsigned gpio, const char *label) 27 27 { 28 if (gpio >= AR7_GPIO_MAX)28 if (gpio >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX)) 29 29 return -EINVAL; 30 30 31 31 if (ar7_gpio_list[gpio]) -
target/linux/ar7/files/arch/mips/ar7/setup.c
23 23 #include <asm/reboot.h> 24 24 #include <asm/time.h> 25 25 #include <asm/ar7/ar7.h> 26 #include <asm/ar7/gpio.h> 26 27 #include <asm/ar7/prom.h> 27 28 29 static int titan_variant; /*hold the results of the gpio_init_titan_variant() so that it is only called once*/ 28 30 static void ar7_machine_restart(char *command); 29 31 static void ar7_machine_halt(void); 30 32 static void ar7_machine_power_off(void); … … 59 61 return "TI AR7 (TNETD7100)"; 60 62 case AR7_CHIP_7200: 61 63 return "TI AR7 (TNETD7200)"; 64 case AR7_CHIP_TITAN: 65 titan_variant = ar7_init_titan_variant(); 66 switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) { 67 case TITAN_CHIP_1050: 68 return "TI AR7 (TNETV1050)"; 69 case TITAN_CHIP_1055: 70 return "TI AR7 (TNETV1055)"; 71 case TITAN_CHIP_1056: 72 return "TI AR7 (TNETV1056)"; 73 case TITAN_CHIP_1060: 74 return "TI AR7 (TNETV1060)"; 75 } 62 76 default: 63 77 return "TI AR7 (Unknown)"; 64 78 } -
target/linux/ar7/files/drivers/char/ar7_gpio.c
98 98 { 99 99 int m = iminor(inode); 100 100 101 if (m >= AR7_GPIO_MAX)101 if (m >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX)) 102 102 return -EINVAL; 103 103 104 104 return nonseekable_open(inode, file); -
target/linux/ar7/patches-2.6.30/930-titan-platform.patch
1 --- a/arch/mips/ar7/platform.c 2009-11-18 14:57:44.000000000 +0800 2 +++ b/arch/mips/ar7/platform.c 2009-11-18 15:43:04.000000000 +0800 3 @@ -128,6 +128,36 @@ 4 }, 5 }; 6 7 +static struct resource cpmac_low_res_titan[] = { 8 + { 9 + .name = "regs", 10 + .flags = IORESOURCE_MEM, 11 + .start = TITAN_REGS_MAC0, 12 + .end = TITAN_REGS_MAC0 + 0x7ff, 13 + }, 14 + { 15 + .name = "irq", 16 + .flags = IORESOURCE_IRQ, 17 + .start = 27, 18 + .end = 27, 19 + }, 20 +}; 21 + 22 +static struct resource cpmac_high_res_titan[] = { 23 + { 24 + .name = "regs", 25 + .flags = IORESOURCE_MEM, 26 + .start = TITAN_REGS_MAC1, 27 + .end = TITAN_REGS_MAC1 + 0x7ff, 28 + }, 29 + { 30 + .name = "irq", 31 + .flags = IORESOURCE_IRQ, 32 + .start = 41, 33 + .end = 41, 34 + }, 35 +}; 36 + 37 static struct resource vlynq_low_res[] = { 38 { 39 .name = "regs", 40 @@ -182,6 +212,60 @@ 41 }, 42 }; 43 44 +static struct resource vlynq_low_res_titan[] = { 45 + { 46 + .name = "regs", 47 + .flags = IORESOURCE_MEM, 48 + .start = TITAN_REGS_VLYNQ0, 49 + .end = TITAN_REGS_VLYNQ0 + 0xff, 50 + }, 51 + { 52 + .name = "irq", 53 + .flags = IORESOURCE_IRQ, 54 + .start = 33, 55 + .end = 33, 56 + }, 57 + { 58 + .name = "mem", 59 + .flags = IORESOURCE_MEM, 60 + .start = 0x0c000000, 61 + .end = 0x0fffffff, 62 + }, 63 + { 64 + .name = "devirq", 65 + .flags = IORESOURCE_IRQ, 66 + .start = 80, 67 + .end = 111, 68 + }, 69 +}; 70 + 71 +static struct resource vlynq_high_res_titan[] = { 72 + { 73 + .name = "regs", 74 + .flags = IORESOURCE_MEM, 75 + .start = TITAN_REGS_VLYNQ1, 76 + .end = TITAN_REGS_VLYNQ1 + 0xff, 77 + }, 78 + { 79 + .name = "irq", 80 + .flags = IORESOURCE_IRQ, 81 + .start = 34, 82 + .end = 34, 83 + }, 84 + { 85 + .name = "mem", 86 + .flags = IORESOURCE_MEM, 87 + .start = 0x40000000, 88 + .end = 0x43ffffff, 89 + }, 90 + { 91 + .name = "devirq", 92 + .flags = IORESOURCE_IRQ, 93 + .start = 112, 94 + .end = 143, 95 + }, 96 +}; 97 + 98 static struct resource usb_res[] = { 99 { 100 .name = "regs", 101 @@ -226,6 +310,18 @@ 102 .phy_mask = 0x7fffffff, 103 }; 104 105 +static struct plat_cpmac_data cpmac_low_data_titan = { 106 + .reset_bit = 17, 107 + .power_bit = 20, 108 + .phy_mask = 0x40000000, 109 +}; 110 + 111 +static struct plat_cpmac_data cpmac_high_data_titan = { 112 + .reset_bit = 21, 113 + .power_bit = 22, 114 + .phy_mask = 0x80000000, 115 +}; 116 + 117 static struct plat_vlynq_data vlynq_low_data = { 118 .ops.on = vlynq_on, 119 .ops.off = vlynq_off, 120 @@ -240,6 +336,20 @@ 121 .gpio_bit = 19, 122 }; 123 124 +static struct plat_vlynq_data vlynq_low_data_titan = { 125 + .ops.on = vlynq_on, 126 + .ops.off = vlynq_off, 127 + .reset_bit = 15, 128 + .gpio_bit = 14, 129 +}; 130 + 131 +static struct plat_vlynq_data vlynq_high_data_titan = { 132 + .ops.on = vlynq_on, 133 + .ops.off = vlynq_off, 134 + .reset_bit = 16, 135 + .gpio_bit = 7, 136 +}; 137 + 138 static struct platform_device physmap_flash = { 139 .id = 0, 140 .name = "physmap-flash", 141 @@ -273,6 +383,30 @@ 142 .num_resources = ARRAY_SIZE(cpmac_high_res), 143 }; 144 145 +static struct platform_device cpmac_low_titan = { 146 + .id = 0, 147 + .name = "cpmac", 148 + .dev = { 149 + .dma_mask = &cpmac_dma_mask, 150 + .coherent_dma_mask = DMA_32BIT_MASK, 151 + .platform_data = &cpmac_low_data_titan, 152 + }, 153 + .resource = cpmac_low_res_titan, 154 + .num_resources = ARRAY_SIZE(cpmac_low_res_titan), 155 +}; 156 + 157 +static struct platform_device cpmac_high_titan = { 158 + .id = 1, 159 + .name = "cpmac", 160 + .dev = { 161 + .dma_mask = &cpmac_dma_mask, 162 + .coherent_dma_mask = DMA_32BIT_MASK, 163 + .platform_data = &cpmac_high_data_titan, 164 + }, 165 + .resource = cpmac_high_res_titan, 166 + .num_resources = ARRAY_SIZE(cpmac_high_res_titan), 167 +}; 168 + 169 static struct platform_device vlynq_low = { 170 .id = 0, 171 .name = "vlynq", 172 @@ -289,6 +423,22 @@ 173 .num_resources = ARRAY_SIZE(vlynq_high_res), 174 }; 175 176 +static struct platform_device vlynq_low_titan = { 177 + .id = 0, 178 + .name = "vlynq", 179 + .dev.platform_data = &vlynq_low_data_titan, 180 + .resource = vlynq_low_res_titan, 181 + .num_resources = ARRAY_SIZE(vlynq_low_res_titan), 182 +}; 183 + 184 +static struct platform_device vlynq_high_titan = { 185 + .id = 1, 186 + .name = "vlynq", 187 + .dev.platform_data = &vlynq_high_data_titan, 188 + .resource = vlynq_high_res_titan, 189 + .num_resources = ARRAY_SIZE(vlynq_high_res_titan), 190 +}; 191 + 192 193 /* This is proper way to define uart ports, but they are then detected 194 * as xscale and, obviously, don't work... 195 @@ -333,6 +483,11 @@ 196 { .name = "status", .gpio = 8, .active_low = 1, }, 197 }; 198 199 +static struct gpio_led titan_leds[] = { 200 + { .name = "status", .gpio = 8, .active_low = 1, }, 201 + { .name = "wifi", .gpio = 13, .active_low = 1, }, 202 +}; 203 + 204 static struct gpio_led dsl502t_leds[] = { 205 { .name = "status", .gpio = 9, .active_low = 1, }, 206 { .name = "ethernet", .gpio = 7, .active_low = 1, }, 207 @@ -425,7 +580,7 @@ 208 /* FIXME: the whole thing is unreliable */ 209 prId = prom_getenv("ProductID"); 210 usb_prod = prom_getenv("usb_prod"); 211 - 212 + 213 /* If we can't get the product id from PROM, use the default LEDs */ 214 if (!prId) 215 return; 216 @@ -442,6 +597,9 @@ 217 } else if (strstr(prId, "DG834")) { 218 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); 219 ar7_led_data.leds = dg834g_leds; 220 + } else if (strstr(prId, "CYWM")) { 221 + ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); 222 + ar7_led_data.leds = titan_leds; 223 } 224 } 225 226 @@ -502,14 +660,18 @@ 227 if (res) 228 return res; 229 230 - ar7_device_disable(vlynq_low_data.reset_bit); 231 - res = platform_device_register(&vlynq_low); 232 + ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit : 233 + vlynq_low_data.reset_bit); 234 + res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan : 235 + &vlynq_low); 236 if (res) 237 return res; 238 239 if (ar7_has_high_vlynq()) { 240 - ar7_device_disable(vlynq_high_data.reset_bit); 241 - res = platform_device_register(&vlynq_high); 242 + ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit : 243 + vlynq_high_data.reset_bit); 244 + res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan : 245 + &vlynq_high); 246 if (res) 247 return res; 248 } -
target/linux/ar7/patches-2.6.30/940-cpmac-titan.patch
1 --- a/arch/mips/ar7/platform.c 2009-11-18 15:47:42.000000000 +0800 2 +++ b/arch/mips/ar7/platform.c 2009-11-19 00:56:05.000000000 +0800 3 @@ -677,24 +677,32 @@ 4 } 5 6 if (ar7_has_high_cpmac()) { 7 - res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); 8 + res = fixed_phy_add(PHY_POLL, ar7_is_titan()?cpmac_high_titan.id: cpmac_high.id, &fixed_phy_status); 9 if (res && res != -ENODEV) 10 return res; 11 12 - cpmac_get_mac(1, cpmac_high_data.dev_addr); 13 - res = platform_device_register(&cpmac_high); 14 + cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr: 15 + cpmac_high_data.dev_addr); 16 + res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan : 17 + &cpmac_high); 18 if (res) 19 return res; 20 } else { 21 - cpmac_low_data.phy_mask = 0xffffffff; 22 - } 23 + if (ar7_is_titan()) 24 + cpmac_low_data_titan.phy_mask = 0xffffffff; 25 + else 26 + cpmac_low_data.phy_mask = 0xffffffff; 27 + } 28 29 - res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); 30 + res = fixed_phy_add(PHY_POLL, ar7_is_titan()?cpmac_low_titan.id: 31 + cpmac_low.id, &fixed_phy_status); 32 if (res && res != -ENODEV) 33 return res; 34 35 - cpmac_get_mac(0, cpmac_low_data.dev_addr); 36 - res = platform_device_register(&cpmac_low); 37 + cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr : 38 + cpmac_low_data.dev_addr); 39 + res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan : 40 + &cpmac_low); 41 if (res) 42 return res; 43 44 --- a/drivers/net/cpmac.c 2009-11-18 15:47:42.000000000 +0800 45 +++ b/drivers/net/cpmac.c 2009-11-19 00:58:25.000000000 +0800 46 @@ -1236,6 +1236,10 @@ 47 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); 48 ar7_device_reset(AR7_RESET_BIT_EPHY); 49 50 + if (ar7_is_titan()) { 51 + ar7_device_reset(TITAN_RESET_BIT_EPHY1); 52 + } 53 + 54 cpmac_mii->reset(cpmac_mii); 55 56 for (i = 0; i < 300; i++) 57 @@ -1250,7 +1254,8 @@ 58 mask = 0; 59 } 60 61 - cpmac_mii->phy_mask = ~(mask | 0x80000000); 62 + cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000): 63 + ~(mask | 0x80000000); 64 snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); 65 66 res = mdiobus_register(cpmac_mii);
